ae805ea907
The way the XICS and the XIVE devices are initialized follows the same pattern. First, try to connect to the KVM device and if not possible fallback on the emulated device, unless a kernel_irqchip is required. The spapr_irq_init_device() routine implements this sequence in generic way using new sPAPR IRQ handlers ->init_emu() and ->init_kvm(). The XIVE init sequence is moved under the associated sPAPR IRQ ->init() handler. This will change again when KVM support is added for the dual interrupt mode. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20190513084245.25755-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
75 lines
2.8 KiB
C
75 lines
2.8 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ backend definitions
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_IRQ_H
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#define HW_SPAPR_IRQ_H
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/*
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* IRQ range offsets per device type
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*/
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#define SPAPR_IRQ_IPI 0x0
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#define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */
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#define SPAPR_IRQ_HOTPLUG 0x1001
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#define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */
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#define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */
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#define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered
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* by the bitmap allocator */
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typedef struct SpaprMachineState SpaprMachineState;
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp);
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
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void spapr_irq_msi_reset(SpaprMachineState *spapr);
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typedef struct SpaprIrq {
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uint32_t nr_irqs;
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uint32_t nr_msis;
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uint8_t ov5;
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void (*init)(SpaprMachineState *spapr, int nr_irqs, Error **errp);
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int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void (*free)(SpaprMachineState *spapr, int irq, int num);
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qemu_irq (*qirq)(SpaprMachineState *spapr, int irq);
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void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
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void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle);
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void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu,
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Error **errp);
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int (*post_load)(SpaprMachineState *spapr, int version_id);
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void (*reset)(SpaprMachineState *spapr, Error **errp);
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void (*set_irq)(void *opaque, int srcno, int val);
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const char *(*get_nodename)(SpaprMachineState *spapr);
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void (*init_emu)(SpaprMachineState *spapr, Error **errp);
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void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
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} SpaprIrq;
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extern SpaprIrq spapr_irq_xics;
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extern SpaprIrq spapr_irq_xics_legacy;
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extern SpaprIrq spapr_irq_xive;
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extern SpaprIrq spapr_irq_dual;
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
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qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
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int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
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void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
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/*
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* XICS legacy routines
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*/
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int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
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#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
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#endif
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