45fefe7c4d
>From observation of various OS sources it can be seen that the token register
introduced in 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" is not
required, since the only register currently implemented is the uninorth hardware
version which is read-only.
Remove the token register implementation and instead return the uninorth
version corresponding to the hardware.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
593 lines
18 KiB
C
593 lines
18 KiB
C
/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/uninorth.h"
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#include "trace.h"
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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static void pci_unin_set_irq(void *opaque, int irq_num, int level)
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{
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UNINHostState *s = opaque;
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trace_unin_set_irq(unin_irq_line[irq_num], level);
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qemu_set_irq(s->irqs[irq_num], level);
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}
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static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
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{
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uint32_t retval;
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if (reg & (1u << 31)) {
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/* XXX OpenBIOS compatibility hack */
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retval = reg | (addr & 3);
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} else if (reg & 1) {
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/* CFA1 style */
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retval = (reg & ~7u) | (addr & 7);
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} else {
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uint32_t slot, func;
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/* Grab CFA0 style values */
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slot = ctz32(reg & 0xfffff800);
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if (slot == 32) {
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slot = -1; /* XXX: should this be 0? */
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}
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func = (reg >> 8) & 7;
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/* ... and then convert them to x86 format */
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/* config pointer */
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retval = (reg & (0xff - 7)) | (addr & 7);
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/* slot */
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retval |= slot << 11;
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/* fn */
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retval |= func << 8;
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}
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trace_unin_get_config_reg(reg, addr, retval);
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return retval;
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}
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static void unin_data_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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UNINHostState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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trace_unin_data_write(addr, len, val);
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pci_data_write(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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val, len);
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}
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static uint64_t unin_data_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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UNINHostState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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uint32_t val;
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val = pci_data_read(phb->bus,
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unin_get_config_reg(phb->config_reg, addr),
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len);
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trace_unin_data_read(addr, len, val);
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return val;
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}
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static const MemoryRegionOps unin_data_ops = {
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.read = unin_data_read,
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.write = unin_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_unin_init_irqs(UNINHostState *s)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
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s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
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}
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}
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static void pci_unin_main_realize(DeviceState *dev, Error **errp)
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{
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UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s,
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&s->pci_mmio,
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&s->pci_io,
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
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pci_unin_init_irqs(s);
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/* DEC 21154 bridge */
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#if 0
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/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
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#endif
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}
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static void pci_unin_main_init(Object *obj)
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{
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UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
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"unin-pci-conf-data", 0x1000);
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memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
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0x100000000ULL);
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memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
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"unin-pci-isa-mmio", 0x00800000);
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memory_region_init_alias(&s->pci_hole, OBJECT(s),
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"unin-pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x10000000ULL);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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sysbus_init_mmio(sbd, &s->pci_hole);
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sysbus_init_mmio(sbd, &s->pci_io);
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}
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static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
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{
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UNINHostState *s = U3_AGP_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s,
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&s->pci_mmio,
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&s->pci_io,
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
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pci_unin_init_irqs(s);
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}
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static void pci_u3_agp_init(Object *obj)
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{
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UNINHostState *s = U3_AGP_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth U3 AGP bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
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"unin-pci-conf-data", 0x1000);
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memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
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0x100000000ULL);
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memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
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"unin-pci-isa-mmio", 0x00800000);
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memory_region_init_alias(&s->pci_hole, OBJECT(s),
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"unin-pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x70000000ULL);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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sysbus_init_mmio(sbd, &s->pci_hole);
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sysbus_init_mmio(sbd, &s->pci_io);
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}
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static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
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{
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UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s,
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&s->pci_mmio,
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&s->pci_io,
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PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
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pci_unin_init_irqs(s);
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}
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static void pci_unin_agp_init(Object *obj)
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{
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UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth AGP bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-agp-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-agp-conf-data", 0x1000);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
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{
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UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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h->bus = pci_register_root_bus(dev, NULL,
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pci_unin_set_irq, pci_unin_map_irq,
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s,
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&s->pci_mmio,
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&s->pci_io,
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PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
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pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
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pci_unin_init_irqs(s);
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}
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static void pci_unin_internal_init(Object *obj)
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{
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UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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/* Uninorth internal bus */
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
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obj, "unin-pci-conf-idx", 0x1000);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
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obj, "unin-pci-conf-data", 0x1000);
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object_property_add_link(obj, "pic", TYPE_OPENPIC,
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(Object **) &s->pic,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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sysbus_init_mmio(sbd, &h->conf_mem);
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sysbus_init_mmio(sbd, &h->data_mem);
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}
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static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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/*
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* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
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* memory space with base 0x80000000, size 0x10000000 for Apple's
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* AppleMacRiscPCI driver
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*/
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d->config[0x48] = 0x0;
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d->config[0x49] = 0x0;
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d->config[0x4a] = 0x0;
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d->config[0x4b] = 0x1;
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}
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static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer
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d->config[0x34] = 0x80; */
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}
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static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache line size */
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d->config[0x0C] = 0x08;
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/* latency timer */
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d->config[0x0D] = 0x10;
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}
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static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
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{
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/* cache_line_size */
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d->config[0x0C] = 0x08;
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/* latency_timer */
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d->config[0x0D] = 0x10;
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/* capabilities_pointer */
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d->config[0x34] = 0x00;
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}
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static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_main_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo unin_main_pci_host_info = {
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.name = "uni-north-pci",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_main_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = u3_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo u3_agp_pci_host_info = {
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.name = "u3-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = u3_agp_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_agp_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo unin_agp_pci_host_info = {
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.name = "uni-north-agp",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_agp_pci_host_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = unin_internal_pci_host_realize;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
|
|
*/
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo unin_internal_pci_host_info = {
|
|
.name = "uni-north-internal-pci",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PCIDevice),
|
|
.class_init = unin_internal_pci_host_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_unin_main_realize;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_main_info = {
|
|
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINHostState),
|
|
.instance_init = pci_unin_main_init,
|
|
.class_init = pci_unin_main_class_init,
|
|
};
|
|
|
|
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_u3_agp_realize;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_u3_agp_info = {
|
|
.name = TYPE_U3_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINHostState),
|
|
.instance_init = pci_u3_agp_init,
|
|
.class_init = pci_u3_agp_class_init,
|
|
};
|
|
|
|
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_unin_agp_realize;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_agp_info = {
|
|
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINHostState),
|
|
.instance_init = pci_unin_agp_init,
|
|
.class_init = pci_unin_agp_class_init,
|
|
};
|
|
|
|
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pci_unin_internal_realize;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pci_unin_internal_info = {
|
|
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(UNINHostState),
|
|
.instance_init = pci_unin_internal_init,
|
|
.class_init = pci_unin_internal_class_init,
|
|
};
|
|
|
|
/* UniN device */
|
|
static void unin_write(void *opaque, hwaddr addr, uint64_t value,
|
|
unsigned size)
|
|
{
|
|
trace_unin_write(addr, value);
|
|
}
|
|
|
|
static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
uint32_t value;
|
|
|
|
switch (addr) {
|
|
case 0:
|
|
value = UNINORTH_VERSION_10A;
|
|
break;
|
|
default:
|
|
value = 0;
|
|
}
|
|
|
|
trace_unin_read(addr, value);
|
|
|
|
return value;
|
|
}
|
|
|
|
static const MemoryRegionOps unin_ops = {
|
|
.read = unin_read,
|
|
.write = unin_write,
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
};
|
|
|
|
static void unin_init(Object *obj)
|
|
{
|
|
UNINState *s = UNI_NORTH(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000);
|
|
|
|
sysbus_init_mmio(sbd, &s->mem);
|
|
}
|
|
|
|
static void unin_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo unin_info = {
|
|
.name = TYPE_UNI_NORTH,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(UNINState),
|
|
.instance_init = unin_init,
|
|
.class_init = unin_class_init,
|
|
};
|
|
|
|
static void unin_register_types(void)
|
|
{
|
|
type_register_static(&unin_main_pci_host_info);
|
|
type_register_static(&u3_agp_pci_host_info);
|
|
type_register_static(&unin_agp_pci_host_info);
|
|
type_register_static(&unin_internal_pci_host_info);
|
|
|
|
type_register_static(&pci_unin_main_info);
|
|
type_register_static(&pci_u3_agp_info);
|
|
type_register_static(&pci_unin_agp_info);
|
|
type_register_static(&pci_unin_internal_info);
|
|
|
|
type_register_static(&unin_info);
|
|
}
|
|
|
|
type_init(unin_register_types)
|