2dfa91a2aa
This is a simple model of the POWER9 XIVE interrupt controller for the PowerNV machine which only addresses the needs of the skiboot firmware. The PowerNV model reuses the common XIVE framework developed for sPAPR as the fundamentals aspects are quite the same. The difference are outlined below. The controller initial BAR configuration is performed using the XSCOM bus from there, MMIO are used for further configuration. The MMIO regions exposed are : - Interrupt controller registers - ESB pages for IPIs and ENDs - Presenter MMIO (Not used) - Thread Interrupt Management Area MMIO, direct and indirect The virtualization controller MMIO region containing the IPI ESB pages and END ESB pages is sub-divided into "sets" which map portions of the VC region to the different ESB pages. These are modeled with custom address spaces and the XiveSource and XiveENDSource objects are sized to the maximum allowed by HW. The memory regions are resized at run-time using the configuration of EDT set translation table provided by the firmware. The XIVE virtualization structure tables (EAT, ENDT, NVTT) are now in the machine RAM and not in the hypervisor anymore. The firmware (skiboot) configures these tables using Virtual Structure Descriptor defining the characteristics of each table : SBE, EAS, END and NVT. These are later used to access the virtual interrupt entries. The internal cache of these tables in the interrupt controller is updated and invalidated using a set of registers. Still to address to complete the model but not fully required is the support for block grouping. Escalation support will be necessary for KVM guests. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/*
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* QEMU PowerPC XIVE interrupt controller model
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*
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* Copyright (c) 2017-2019, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_PNV_XIVE_H
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#define PPC_PNV_XIVE_H
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#include "hw/ppc/xive.h"
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struct PnvChip;
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#define TYPE_PNV_XIVE "pnv-xive"
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#define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE)
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#define XIVE_BLOCK_MAX 16
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#define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
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#define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */
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#define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
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#define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
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typedef struct PnvXive {
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XiveRouter parent_obj;
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/* Owning chip */
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struct PnvChip *chip;
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/* XSCOM addresses giving access to the controller registers */
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MemoryRegion xscom_regs;
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/* Main MMIO regions that can be configured by FW */
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MemoryRegion ic_mmio;
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MemoryRegion ic_reg_mmio;
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MemoryRegion ic_notify_mmio;
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MemoryRegion ic_lsi_mmio;
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MemoryRegion tm_indirect_mmio;
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MemoryRegion vc_mmio;
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MemoryRegion pc_mmio;
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MemoryRegion tm_mmio;
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/*
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* IPI and END address spaces modeling the EDT segmentation in the
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* VC region
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*/
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AddressSpace ipi_as;
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MemoryRegion ipi_mmio;
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MemoryRegion ipi_edt_mmio;
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AddressSpace end_as;
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MemoryRegion end_mmio;
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MemoryRegion end_edt_mmio;
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/* Shortcut values for the Main MMIO regions */
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hwaddr ic_base;
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uint32_t ic_shift;
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hwaddr vc_base;
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uint32_t vc_shift;
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hwaddr pc_base;
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uint32_t pc_shift;
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hwaddr tm_base;
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uint32_t tm_shift;
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/* Our XIVE source objects for IPIs and ENDs */
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XiveSource ipi_source;
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XiveENDSource end_source;
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/* Interrupt controller registers */
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uint64_t regs[0x300];
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/* Can be configured by FW */
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uint32_t tctx_chipid;
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/*
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* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
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* These are in a SRAM protected by ECC.
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*/
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uint64_t vsds[5][XIVE_BLOCK_MAX];
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/* Translation tables */
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uint64_t blk[XIVE_TABLE_BLK_MAX];
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uint64_t mig[XIVE_TABLE_MIG_MAX];
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uint64_t vdt[XIVE_TABLE_VDT_MAX];
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uint64_t edt[XIVE_TABLE_EDT_MAX];
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} PnvXive;
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void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
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#endif /* PPC_PNV_XIVE_H */
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