b8a9e8f133
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/*
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* ARM execution defines
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "dyngen-exec.h"
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register struct CPUARMState *env asm(AREG0);
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register uint32_t T0 asm(AREG1);
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register uint32_t T1 asm(AREG2);
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register uint32_t T2 asm(AREG3);
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#include "cpu.h"
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#include "exec-all.h"
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void cpu_lock(void);
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void cpu_unlock(void);
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void cpu_loop_exit(void);
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/* Implemented CPSR bits. */
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#define CACHED_CPSR_BITS 0xf8000000
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static inline int compute_cpsr(void)
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{
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int ZF;
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ZF = (env->NZF == 0);
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return env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
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(env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27);
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}
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static inline void env_to_regs(void)
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{
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}
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static inline void regs_to_env(void)
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{
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}
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu);
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