c5c0fdbe39
commit 7e364e56293bb98cae1b55fd835f5991c4e96e7d Signed-off-by: David 'Digit' Turner <digit@google.com> Message-Id: <20230405172109.3081788-4-digit@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
464 lines
15 KiB
C
464 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/uapi/asm/kvm.h:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#define KVM_SPSR_EL1 0
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#define KVM_SPSR_SVC KVM_SPSR_EL1
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#define KVM_SPSR_ABT 1
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#define KVM_SPSR_UND 2
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#define KVM_SPSR_IRQ 3
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#define KVM_SPSR_FIQ 4
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#define KVM_NR_SPSR 5
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#ifndef __ASSEMBLY__
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#include <linux/psci.h>
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#include <linux/types.h>
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#include <asm/ptrace.h>
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#include <asm/sve_context.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_READONLY_MEM
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#define __KVM_HAVE_VCPU_EVENTS
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_DIRTY_LOG_PAGE_OFFSET 64
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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struct kvm_regs {
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struct user_pt_regs regs; /* sp = sp_el0 */
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__u64 sp_el1;
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__u64 elr_el1;
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__u64 spsr[KVM_NR_SPSR];
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struct user_fpsimd_state fp_regs;
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};
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/*
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* Supported CPU Targets - Adding a new target type is not recommended,
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* unless there are some special registers not supported by the
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* genericv8 syreg table.
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*/
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#define KVM_ARM_TARGET_AEM_V8 0
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#define KVM_ARM_TARGET_FOUNDATION_V8 1
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#define KVM_ARM_TARGET_CORTEX_A57 2
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#define KVM_ARM_TARGET_XGENE_POTENZA 3
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#define KVM_ARM_TARGET_CORTEX_A53 4
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/* Generic ARM v8 target */
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#define KVM_ARM_TARGET_GENERIC_V8 5
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#define KVM_ARM_NUM_TARGETS 6
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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#define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
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KVM_ARM_DEVICE_TYPE_SHIFT)
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#define KVM_ARM_DEVICE_ID_SHIFT 16
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#define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
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KVM_ARM_DEVICE_ID_SHIFT)
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/* Supported device IDs */
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#define KVM_ARM_DEVICE_VGIC_V2 0
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/* Supported VGIC address types */
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#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
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#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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/* Supported VGICv3 address types */
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_ITS_ADDR_TYPE 4
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
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#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
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#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
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#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
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#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
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#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
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#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
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struct kvm_vcpu_init {
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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};
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struct kvm_fpu {
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};
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/*
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* See v8 ARM ARM D7.3: Debug Registers
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*
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* The architectural limit is 16 debug registers of each type although
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* in practice there are usually less (see ID_AA64DFR0_EL1).
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*
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* Although the control registers are architecturally defined as 32
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* bits wide we use a 64 bit structure here to keep parity with
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* KVM_GET/SET_ONE_REG behaviour which treats all system registers as
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* 64 bit values. It also allows for the possibility of the
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* architecture expanding the control registers without having to
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* change the userspace ABI.
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*/
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#define KVM_ARM_MAX_DBG_REGS 16
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struct kvm_guest_debug_arch {
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__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
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__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
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__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
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__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
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};
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#define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0)
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struct kvm_debug_exit_arch {
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__u32 hsr;
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__u32 hsr_high; /* ESR_EL2[61:32] */
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__u64 far; /* used for watchpoints */
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};
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/*
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* Architecture specific defines for kvm_guest_debug->control
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*/
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#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
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#define KVM_GUESTDBG_USE_HW (1 << 17)
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struct kvm_sync_regs {
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/* Used with KVM_CAP_ARM_USER_IRQ */
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__u64 device_irq_level;
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};
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/*
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* PMU filter structure. Describe a range of events with a particular
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* action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
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*/
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struct kvm_pmu_event_filter {
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__u16 base_event;
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__u16 nevents;
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#define KVM_PMU_EVENT_ALLOW 0
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#define KVM_PMU_EVENT_DENY 1
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__u8 action;
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__u8 pad[3];
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};
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/* for KVM_GET/SET_VCPU_EVENTS */
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struct kvm_vcpu_events {
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struct {
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__u8 serror_pending;
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__u8 serror_has_esr;
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__u8 ext_dabt_pending;
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/* Align it to 8 bytes */
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__u8 pad[5];
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__u64 serror_esr;
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} exception;
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__u32 reserved[12];
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};
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struct kvm_arm_copy_mte_tags {
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__u64 guest_ipa;
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__u64 length;
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void *addr;
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__u64 flags;
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__u64 reserved[2];
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};
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#define KVM_ARM_TAGS_TO_GUEST 0
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#define KVM_ARM_TAGS_FROM_GUEST 1
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define KVM_REG_ARM_COPROC_SHIFT 16
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
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/* Some registers need more space to represent values. */
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#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
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#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
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#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
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#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
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#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
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/* AArch64 system registers */
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#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
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#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
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#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
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#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
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#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
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#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
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#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
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#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
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#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
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#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
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(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
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KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
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#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
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ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
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ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
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ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
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ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
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ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
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#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
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/* Physical Timer EL0 Registers */
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#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
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#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
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#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
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/*
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* EL0 Virtual Timer Registers
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*
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* WARNING:
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* KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
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* with the appropriate register encodings. Their values have been
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* accidentally swapped. As this is set API, the definitions here
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* must be used, rather than ones derived from the encodings.
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*/
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#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
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#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
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/* KVM-as-firmware specific pseudo-registers */
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#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
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KVM_REG_ARM_FW | ((r) & 0xffff))
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#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
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/*
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* Only two states can be presented by the host kernel:
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* - NOT_REQUIRED: the guest doesn't need to do anything
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* - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
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*
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* All the other values are deprecated. The host still accepts all
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* values (they are ABI), but will narrow them to the above two.
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*/
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3)
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1
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#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2
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/* SVE registers */
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#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
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/* Z- and P-regs occupy blocks at the following offsets within this range: */
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#define KVM_REG_ARM64_SVE_ZREG_BASE 0
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#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
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#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
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#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
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#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
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#define KVM_ARM64_SVE_MAX_SLICES 32
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#define KVM_REG_ARM64_SVE_ZREG(n, i) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
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KVM_REG_SIZE_U2048 | \
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(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \
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((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
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#define KVM_REG_ARM64_SVE_PREG(n, i) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
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KVM_REG_SIZE_U256 | \
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(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \
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((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
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#define KVM_REG_ARM64_SVE_FFR(i) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
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KVM_REG_SIZE_U256 | \
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((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
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/*
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* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
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* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
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* invariant layout which differs from the layout used for the FPSIMD
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* V-registers on big-endian systems: see sigcontext.h for more explanation.
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*/
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#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
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#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
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/* Vector lengths pseudo-register: */
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#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
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KVM_REG_SIZE_U512 | 0xffff)
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#define KVM_ARM64_SVE_VLS_WORDS \
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((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
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/* Bitmap feature firmware registers */
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#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
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KVM_REG_ARM_FW_FEAT_BMAP | \
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((r) & 0xffff))
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#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0)
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enum {
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KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0,
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};
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#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1)
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enum {
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KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0,
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};
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#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2)
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enum {
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KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0,
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KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1,
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};
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/* Device Control API: ARM VGIC */
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#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
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#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
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(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
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#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
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#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
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#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
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#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
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(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
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#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
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#define VGIC_LEVEL_INFO_LINE_LEVEL 0
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_ITS_CTRL_RESET 4
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/* Device Control API on vcpu fd */
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#define KVM_ARM_VCPU_PMU_V3_CTRL 0
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#define KVM_ARM_VCPU_PMU_V3_IRQ 0
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#define KVM_ARM_VCPU_PMU_V3_INIT 1
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#define KVM_ARM_VCPU_PMU_V3_FILTER 2
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#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3
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#define KVM_ARM_VCPU_TIMER_CTRL 1
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#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
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#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
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#define KVM_ARM_VCPU_PVTIME_CTRL 2
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#define KVM_ARM_VCPU_PVTIME_IPA 0
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_VCPU2_SHIFT 28
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#define KVM_ARM_IRQ_VCPU2_MASK 0xf
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xf
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#define KVM_ARM_IRQ_VCPU_SHIFT 16
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#define KVM_ARM_IRQ_VCPU_MASK 0xff
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#define KVM_ARM_IRQ_NUM_SHIFT 0
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#define KVM_ARM_IRQ_NUM_MASK 0xffff
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/* irq_type field */
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#define KVM_ARM_IRQ_TYPE_CPU 0
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#define KVM_ARM_IRQ_TYPE_SPI 1
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#define KVM_ARM_IRQ_TYPE_PPI 2
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/* out-of-kernel GIC cpu interrupt injection irq_number field */
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/*
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* This used to hold the highest supported SPI, but it is now obsolete
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* and only here to provide source code level compatibility with older
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* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
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*/
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#define KVM_ARM_IRQ_GIC_MAX 127
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/* One single KVM irqchip, ie. the VGIC */
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#define KVM_NR_IRQCHIPS 1
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/* PSCI interface */
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
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#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
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#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
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#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
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#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
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#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
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#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
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#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
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/* arm64-specific kvm_run::system_event flags */
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/*
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* Reset caused by a PSCI v1.1 SYSTEM_RESET2 call.
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* Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET.
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*/
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#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0)
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/* run->fail_entry.hardware_entry_failure_reason codes. */
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#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0)
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#endif
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#endif /* __ARM_KVM_H__ */
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