qemu-e2k/target
Alex Bennée 102661430c target/mips: simplify gen_compute_imm_branch logic
One of the Travis builds was complaining about:

  qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
       return (TCGCond)(c ^ 1);
  ../target/mips/translate.c:20031:13: note: ‘cond’ was declared here
       TCGCond cond;

Rather than figure out exactly which one was causing the complaint I
just defaulted to TCG_COND_ALWAYS and allowed that state to double up
for the now defunct bcond_compute variable.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200909112742.25730-5-alex.bennee@linaro.org>
2020-09-10 10:43:57 +01:00
..
alpha meson: target 2020-08-21 06:30:35 -04:00
arm target/arm: Move setting of CPU halted state to generic code 2020-09-08 10:08:42 +10:00
avr meson: target 2020-08-21 06:30:35 -04:00
cris target/cris: Remove superfluous breaks 2020-09-01 08:41:15 +02:00
hppa target/hppa: Fix boot with old Linux installation CDs 2020-09-02 23:16:57 +02:00
i386 target/i386/sev: Plug memleak in sev_read_file_base64 2020-09-02 07:30:26 -04:00
lm32 meson: target 2020-08-21 06:30:35 -04:00
m68k meson: target 2020-08-21 06:30:35 -04:00
microblaze target/microblaze: Put MicroBlazeCPUConfig into DisasContext 2020-09-07 12:58:08 -07:00
mips target/mips: simplify gen_compute_imm_branch logic 2020-09-10 10:43:57 +01:00
moxie meson: target 2020-08-21 06:30:35 -04:00
nios2 meson: target 2020-08-21 06:30:35 -04:00
openrisc meson: target 2020-08-21 06:30:35 -04:00
ppc target/ppc: Remove superfluous breaks 2020-09-01 08:34:08 +02:00
riscv softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00
rx rx: Move typedef RXCPU to cpu-qom.h 2020-09-02 07:29:25 -04:00
s390x target/s390x: Use start-powered-off CPUState property 2020-09-08 10:08:43 +10:00
sh4 target/sh4: Remove superfluous breaks 2020-09-01 08:38:41 +02:00
sparc meson: target 2020-08-21 06:30:35 -04:00
tilegx meson: target 2020-08-21 06:30:35 -04:00
tricore meson: target 2020-08-21 06:30:35 -04:00
unicore32 meson: target 2020-08-21 06:30:35 -04:00
xtensa target/xtensa: import DSP3400 core 2020-08-21 12:56:45 -07:00
meson.build meson: target 2020-08-21 06:30:35 -04:00