Yifei Jiang c63ca4ff7f target/riscv: Fix the bug of HLVX/HLV/HSV ... We found that the hypervisor virtual-machine load and store instructions, included HLVX/HLV/HSV, couldn't access guest userspace memory. In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow: "As usual when V=1, two-stage address translation is applied, and the HS-level sstatus.SUM is ignored." But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV accesses guest userspace memory. So this patch fixes it. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201130012810.899-1-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-12-17 21:56:43 -08:00
..
insn_trans	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
cpu_bits.h	target/riscv: Remove the HS_TWO_STAGE flag	2020-11-09 15:08:53 -08:00
cpu_helper.c	target/riscv: Fix the bug of HLVX/HLV/HSV	2020-12-17 21:56:43 -08:00
cpu_user.h
cpu-param.h	target/riscv: Add a virtualised MMU Mode	2020-11-09 15:08:45 -08:00
cpu.c	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
cpu.h	target/riscv: Remove the hyp load and store functions	2020-11-09 15:08:57 -08:00
csr.c	target/riscv/csr.c : add space before the open parenthesis '('	2020-11-03 07:17:23 -08:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2020-08-21 22:37:55 -07:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h
internals.h	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
machine.c	target/riscv: Add V extension state description	2020-11-03 07:17:23 -08:00
meson.build	target/riscv: Add basic vmstate description of CPU	2020-11-03 07:17:23 -08:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	target/riscv: Split the Hypervisor execute load helpers	2020-11-09 15:09:00 -08:00
pmp.c	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
pmp.h	target/riscv: Add PMP state description	2020-11-03 07:17:23 -08:00
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Remove the hyp load and store functions	2020-11-09 15:08:57 -08:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00