Pavel Dovgalyuk c6c2c0fc32 mips: set CP0 Debug DExcCode for SDBBP instruction ... This patch fixes setting DExcCode field of CP0 Debug register when SDBBP instruction is executed. According to EJTAG specification, this field must be set to the value 9 (Bp). Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-id: 20170502120350.3368.92338.stgit@PASHA-ISP Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2017-07-17 16:48:21 +02:00
..
cpu-qom.h
cpu.c
cpu.h	target-mips: Provide function to test if a CPU supports an ISA	2017-02-21 22:24:58 +00:00
dsp_helper.c
gdbstub.c
helper.c	mips: set CP0 Debug DExcCode for SDBBP instruction	2017-07-17 16:48:21 +02:00
helper.h
kvm_mips.h
kvm.c	vcpu_dirty: share the same field in CPUState for all accelerators	2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c	migration: extend VMStateInfo	2017-01-24 17:54:47 +00:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target/mips: hold BQL for timer interrupts	2017-03-09 10:41:48 +00:00
TODO
trace-events	target-mips: replace few LOG_DISAS() with trace points	2017-03-20 11:06:32 +00:00
translate_init.c
translate.c	target/mips: fix msa copy_[s|u]_df rd = 0 corner case	2017-07-11 15:06:34 +01:00