1052 lines
32 KiB
C
1052 lines
32 KiB
C
/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/char/serial.h"
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#include "chardev/char-serial.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
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#define UART_IIR_FE 0xC0 /* Fifo enabled */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
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#define UART_FCR_FE 0x01 /* FIFO Enable */
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#define MAX_XMIT_RETRY 4
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#ifdef DEBUG_SERIAL
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do {} while (0)
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#endif
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static void serial_receive1(void *opaque, const uint8_t *buf, int size);
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static void serial_xmit(SerialState *s);
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static inline void recv_fifo_put(SerialState *s, uint8_t chr)
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{
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/* Receive overruns do not overwrite FIFO contents. */
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if (!fifo8_is_full(&s->recv_fifo)) {
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fifo8_push(&s->recv_fifo, chr);
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} else {
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s->lsr |= UART_LSR_OE;
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}
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}
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static void serial_update_irq(SerialState *s)
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{
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uint8_t tmp_iir = UART_IIR_NO_INT;
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI;
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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tmp_iir = UART_IIR_CTI;
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
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(!(s->fcr & UART_FCR_FE) ||
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s->recv_fifo.num >= s->recv_fifo_itl)) {
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tmp_iir = UART_IIR_RDI;
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
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tmp_iir = UART_IIR_THRI;
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
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tmp_iir = UART_IIR_MSI;
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}
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void serial_update_parameters(SerialState *s)
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{
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp;
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if (s->divider == 0 || s->divider > s->baudbase) {
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return;
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}
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/* Start bit. */
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frame_size = 1;
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if (s->lcr & 0x08) {
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/* Parity bit. */
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frame_size++;
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if (s->lcr & 0x10)
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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}
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if (s->lcr & 0x04)
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5;
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frame_size += data_bits + stop_bits;
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speed = s->baudbase / s->divider;
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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}
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static void serial_update_msl(SerialState *s)
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{
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uint8_t omsr;
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int flags;
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timer_del(s->modem_status_poll);
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if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
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&flags) == -ENOTSUP) {
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s->poll_msl = -1;
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return;
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}
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omsr = s->msr;
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI;
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serial_update_irq(s);
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}
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl) {
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timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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NANOSECONDS_PER_SECOND / 100);
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}
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}
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static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
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void *opaque)
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{
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SerialState *s = opaque;
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s->watch_tag = 0;
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serial_xmit(s);
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return FALSE;
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}
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static void serial_xmit(SerialState *s)
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{
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do {
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assert(!(s->lsr & UART_LSR_TEMT));
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if (s->tsr_retry == 0) {
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assert(!(s->lsr & UART_LSR_THRE));
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if (s->fcr & UART_FCR_FE) {
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assert(!fifo8_is_empty(&s->xmit_fifo));
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s->tsr = fifo8_pop(&s->xmit_fifo);
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if (!s->xmit_fifo.num) {
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s->lsr |= UART_LSR_THRE;
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}
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} else {
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s->tsr = s->thr;
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s->lsr |= UART_LSR_THRE;
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}
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if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
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s->thr_ipending = 1;
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serial_update_irq(s);
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}
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}
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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} else if (qemu_chr_fe_write(&s->chr, &s->tsr, 1) != 1 &&
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s->tsr_retry < MAX_XMIT_RETRY) {
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assert(s->watch_tag == 0);
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s->watch_tag =
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qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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serial_watch_cb, s);
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if (s->watch_tag > 0) {
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s->tsr_retry++;
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return;
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}
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}
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s->tsr_retry = 0;
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/* Transmit another byte if it is already available. It is only
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possible when FIFO is enabled and not empty. */
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} while (!(s->lsr & UART_LSR_THRE));
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s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->lsr |= UART_LSR_TEMT;
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}
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/* Setter for FCR.
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is_load flag means, that value is set while loading VM state
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and interrupt should not be invoked */
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static void serial_write_fcr(SerialState *s, uint8_t val)
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{
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/* Set fcr - val only has the bits that are supposed to "stick" */
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s->fcr = val;
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if (val & UART_FCR_FE) {
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s->iir |= UART_IIR_FE;
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/* Set recv_fifo trigger Level */
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switch (val & 0xC0) {
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case UART_FCR_ITL_1:
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s->recv_fifo_itl = 1;
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break;
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case UART_FCR_ITL_2:
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s->recv_fifo_itl = 4;
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break;
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case UART_FCR_ITL_3:
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s->recv_fifo_itl = 8;
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break;
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case UART_FCR_ITL_4:
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s->recv_fifo_itl = 14;
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break;
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}
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} else {
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s->iir &= ~UART_IIR_FE;
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}
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}
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static void serial_update_tiocm(SerialState *s)
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{
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int flags;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
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flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
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if (s->mcr & UART_MCR_RTS) {
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flags |= CHR_TIOCM_RTS;
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}
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if (s->mcr & UART_MCR_DTR) {
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flags |= CHR_TIOCM_DTR;
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}
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
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}
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static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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SerialState *s = opaque;
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addr &= 7;
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DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
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switch(addr) {
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default:
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case 0:
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0xff00) | val;
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serial_update_parameters(s);
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} else {
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s->thr = (uint8_t) val;
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if(s->fcr & UART_FCR_FE) {
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/* xmit overruns overwrite data, so make space if needed */
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if (fifo8_is_full(&s->xmit_fifo)) {
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fifo8_pop(&s->xmit_fifo);
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}
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fifo8_push(&s->xmit_fifo, s->thr);
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}
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s->thr_ipending = 0;
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s->lsr &= ~UART_LSR_THRE;
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s->lsr &= ~UART_LSR_TEMT;
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serial_update_irq(s);
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if (s->tsr_retry == 0) {
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serial_xmit(s);
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}
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}
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break;
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case 1:
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if (s->lcr & UART_LCR_DLAB) {
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s->divider = (s->divider & 0x00ff) | (val << 8);
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serial_update_parameters(s);
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} else {
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uint8_t changed = (s->ier ^ val) & 0x0f;
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s->ier = val & 0x0f;
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/* If the backend device is a real serial port, turn polling of the modem
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* status lines on physical port on or off depending on UART_IER_MSI state.
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*/
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if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
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if (s->ier & UART_IER_MSI) {
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s->poll_msl = 1;
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serial_update_msl(s);
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} else {
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timer_del(s->modem_status_poll);
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s->poll_msl = 0;
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}
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}
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/* Turning on the THRE interrupt on IER can trigger the interrupt
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* if LSR.THRE=1, even if it had been masked before by reading IIR.
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* This is not in the datasheet, but Windows relies on it. It is
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* unclear if THRE has to be resampled every time THRI becomes
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* 1, or only on the rising edge. Bochs does the latter, and Windows
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* always toggles IER to all zeroes and back to all ones, so do the
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* same.
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*
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* If IER.THRI is zero, thr_ipending is not used. Set it to zero
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* so that the thr_ipending subsection is not migrated.
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*/
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if (changed & UART_IER_THRI) {
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if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
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s->thr_ipending = 1;
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} else {
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s->thr_ipending = 0;
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}
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}
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if (changed) {
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serial_update_irq(s);
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}
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}
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break;
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case 2:
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/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
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if ((val ^ s->fcr) & UART_FCR_FE) {
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val |= UART_FCR_XFR | UART_FCR_RFR;
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}
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/* FIFO clear */
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if (val & UART_FCR_RFR) {
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s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
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timer_del(s->fifo_timeout_timer);
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s->timeout_ipending = 0;
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fifo8_reset(&s->recv_fifo);
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}
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if (val & UART_FCR_XFR) {
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s->lsr |= UART_LSR_THRE;
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s->thr_ipending = 1;
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fifo8_reset(&s->xmit_fifo);
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}
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serial_write_fcr(s, val & 0xC9);
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serial_update_irq(s);
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break;
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case 3:
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{
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int break_enable;
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s->lcr = val;
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serial_update_parameters(s);
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break_enable = (val >> 6) & 1;
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if (break_enable != s->last_break_enable) {
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s->last_break_enable = break_enable;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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&break_enable);
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}
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}
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break;
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case 4:
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{
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int old_mcr = s->mcr;
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s->mcr = val & 0x1f;
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if (val & UART_MCR_LOOP)
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break;
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|
|
if (s->poll_msl >= 0 && old_mcr != s->mcr) {
|
|
serial_update_tiocm(s);
|
|
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
|
from the device/computer at the other end of the serial line */
|
|
timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
|
|
}
|
|
}
|
|
break;
|
|
case 5:
|
|
break;
|
|
case 6:
|
|
break;
|
|
case 7:
|
|
s->scr = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
SerialState *s = opaque;
|
|
uint32_t ret;
|
|
|
|
addr &= 7;
|
|
switch(addr) {
|
|
default:
|
|
case 0:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = s->divider & 0xff;
|
|
} else {
|
|
if(s->fcr & UART_FCR_FE) {
|
|
ret = fifo8_is_empty(&s->recv_fifo) ?
|
|
0 : fifo8_pop(&s->recv_fifo);
|
|
if (s->recv_fifo.num == 0) {
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
} else {
|
|
timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
|
|
}
|
|
s->timeout_ipending = 0;
|
|
} else {
|
|
ret = s->rbr;
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
}
|
|
serial_update_irq(s);
|
|
if (!(s->mcr & UART_MCR_LOOP)) {
|
|
/* in loopback mode, don't receive any data */
|
|
qemu_chr_fe_accept_input(&s->chr);
|
|
}
|
|
}
|
|
break;
|
|
case 1:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = (s->divider >> 8) & 0xff;
|
|
} else {
|
|
ret = s->ier;
|
|
}
|
|
break;
|
|
case 2:
|
|
ret = s->iir;
|
|
if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
|
|
s->thr_ipending = 0;
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 3:
|
|
ret = s->lcr;
|
|
break;
|
|
case 4:
|
|
ret = s->mcr;
|
|
break;
|
|
case 5:
|
|
ret = s->lsr;
|
|
/* Clear break and overrun interrupts */
|
|
if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
|
|
s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 6:
|
|
if (s->mcr & UART_MCR_LOOP) {
|
|
/* in loopback, the modem output pins are connected to the
|
|
inputs */
|
|
ret = (s->mcr & 0x0c) << 4;
|
|
ret |= (s->mcr & 0x02) << 3;
|
|
ret |= (s->mcr & 0x01) << 5;
|
|
} else {
|
|
if (s->poll_msl >= 0)
|
|
serial_update_msl(s);
|
|
ret = s->msr;
|
|
/* Clear delta bits & msr int after read, if they were set */
|
|
if (s->msr & UART_MSR_ANY_DELTA) {
|
|
s->msr &= 0xF0;
|
|
serial_update_irq(s);
|
|
}
|
|
}
|
|
break;
|
|
case 7:
|
|
ret = s->scr;
|
|
break;
|
|
}
|
|
DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
|
|
return ret;
|
|
}
|
|
|
|
static int serial_can_receive(SerialState *s)
|
|
{
|
|
if(s->fcr & UART_FCR_FE) {
|
|
if (s->recv_fifo.num < UART_FIFO_LENGTH) {
|
|
/*
|
|
* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
|
|
* if above. If UART_FIFO_LENGTH - fifo.count is advertised the
|
|
* effect will be to almost always fill the fifo completely before
|
|
* the guest has a chance to respond, effectively overriding the ITL
|
|
* that the guest has set.
|
|
*/
|
|
return (s->recv_fifo.num <= s->recv_fifo_itl) ?
|
|
s->recv_fifo_itl - s->recv_fifo.num : 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
} else {
|
|
return !(s->lsr & UART_LSR_DR);
|
|
}
|
|
}
|
|
|
|
static void serial_receive_break(SerialState *s)
|
|
{
|
|
s->rbr = 0;
|
|
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
|
recv_fifo_put(s, '\0');
|
|
s->lsr |= UART_LSR_BI | UART_LSR_DR;
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
|
static void fifo_timeout_int (void *opaque) {
|
|
SerialState *s = opaque;
|
|
if (s->recv_fifo.num) {
|
|
s->timeout_ipending = 1;
|
|
serial_update_irq(s);
|
|
}
|
|
}
|
|
|
|
static int serial_can_receive1(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
return serial_can_receive(s);
|
|
}
|
|
|
|
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
if (s->wakeup) {
|
|
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
|
|
}
|
|
if(s->fcr & UART_FCR_FE) {
|
|
int i;
|
|
for (i = 0; i < size; i++) {
|
|
recv_fifo_put(s, buf[i]);
|
|
}
|
|
s->lsr |= UART_LSR_DR;
|
|
/* call the timeout receive callback in 4 char transmit time */
|
|
timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
|
|
} else {
|
|
if (s->lsr & UART_LSR_DR)
|
|
s->lsr |= UART_LSR_OE;
|
|
s->rbr = buf[0];
|
|
s->lsr |= UART_LSR_DR;
|
|
}
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
static void serial_event(void *opaque, int event)
|
|
{
|
|
SerialState *s = opaque;
|
|
DPRINTF("event %x\n", event);
|
|
if (event == CHR_EVENT_BREAK)
|
|
serial_receive_break(s);
|
|
}
|
|
|
|
static int serial_pre_save(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
s->fcr_vmstate = s->fcr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_pre_load(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
s->thr_ipending = -1;
|
|
s->poll_msl = -1;
|
|
return 0;
|
|
}
|
|
|
|
static int serial_post_load(void *opaque, int version_id)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
if (version_id < 3) {
|
|
s->fcr_vmstate = 0;
|
|
}
|
|
if (s->thr_ipending == -1) {
|
|
s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
|
|
}
|
|
|
|
if (s->tsr_retry > 0) {
|
|
/* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */
|
|
if (s->lsr & UART_LSR_TEMT) {
|
|
error_report("inconsistent state in serial device "
|
|
"(tsr empty, tsr_retry=%d", s->tsr_retry);
|
|
return -1;
|
|
}
|
|
|
|
if (s->tsr_retry > MAX_XMIT_RETRY) {
|
|
s->tsr_retry = MAX_XMIT_RETRY;
|
|
}
|
|
|
|
assert(s->watch_tag == 0);
|
|
s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
|
|
serial_watch_cb, s);
|
|
} else {
|
|
/* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */
|
|
if (!(s->lsr & UART_LSR_TEMT)) {
|
|
error_report("inconsistent state in serial device "
|
|
"(tsr not empty, tsr_retry=0");
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
s->last_break_enable = (s->lcr >> 6) & 1;
|
|
/* Initialize fcr via setter to perform essential side-effects */
|
|
serial_write_fcr(s, s->fcr_vmstate);
|
|
serial_update_parameters(s);
|
|
return 0;
|
|
}
|
|
|
|
static bool serial_thr_ipending_needed(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
if (s->ier & UART_IER_THRI) {
|
|
bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
|
|
return s->thr_ipending != expected_value;
|
|
} else {
|
|
/* LSR.THRE will be sampled again when the interrupt is
|
|
* enabled. thr_ipending is not used in this case, do
|
|
* not migrate it.
|
|
*/
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_thr_ipending = {
|
|
.name = "serial/thr_ipending",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_thr_ipending_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32(thr_ipending, SerialState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_tsr_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return s->tsr_retry != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_tsr = {
|
|
.name = "serial/tsr",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_tsr_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(tsr_retry, SerialState),
|
|
VMSTATE_UINT8(thr, SerialState),
|
|
VMSTATE_UINT8(tsr, SerialState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_recv_fifo_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return !fifo8_is_empty(&s->recv_fifo);
|
|
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_recv_fifo = {
|
|
.name = "serial/recv_fifo",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_recv_fifo_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_xmit_fifo_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return !fifo8_is_empty(&s->xmit_fifo);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_xmit_fifo = {
|
|
.name = "serial/xmit_fifo",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_xmit_fifo_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_fifo_timeout_timer_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return timer_pending(s->fifo_timeout_timer);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
|
|
.name = "serial/fifo_timeout_timer",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_fifo_timeout_timer_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_timeout_ipending_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return s->timeout_ipending != 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_timeout_ipending = {
|
|
.name = "serial/timeout_ipending",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = serial_timeout_ipending_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32(timeout_ipending, SerialState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static bool serial_poll_needed(void *opaque)
|
|
{
|
|
SerialState *s = (SerialState *)opaque;
|
|
return s->poll_msl >= 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_serial_poll = {
|
|
.name = "serial/poll",
|
|
.version_id = 1,
|
|
.needed = serial_poll_needed,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32(poll_msl, SerialState),
|
|
VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
const VMStateDescription vmstate_serial = {
|
|
.name = "serial",
|
|
.version_id = 3,
|
|
.minimum_version_id = 2,
|
|
.pre_save = serial_pre_save,
|
|
.pre_load = serial_pre_load,
|
|
.post_load = serial_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT16_V(divider, SerialState, 2),
|
|
VMSTATE_UINT8(rbr, SerialState),
|
|
VMSTATE_UINT8(ier, SerialState),
|
|
VMSTATE_UINT8(iir, SerialState),
|
|
VMSTATE_UINT8(lcr, SerialState),
|
|
VMSTATE_UINT8(mcr, SerialState),
|
|
VMSTATE_UINT8(lsr, SerialState),
|
|
VMSTATE_UINT8(msr, SerialState),
|
|
VMSTATE_UINT8(scr, SerialState),
|
|
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&vmstate_serial_thr_ipending,
|
|
&vmstate_serial_tsr,
|
|
&vmstate_serial_recv_fifo,
|
|
&vmstate_serial_xmit_fifo,
|
|
&vmstate_serial_fifo_timeout_timer,
|
|
&vmstate_serial_timeout_ipending,
|
|
&vmstate_serial_poll,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
static void serial_reset(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
if (s->watch_tag > 0) {
|
|
g_source_remove(s->watch_tag);
|
|
s->watch_tag = 0;
|
|
}
|
|
|
|
s->rbr = 0;
|
|
s->ier = 0;
|
|
s->iir = UART_IIR_NO_INT;
|
|
s->lcr = 0;
|
|
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
|
|
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
|
|
/* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
|
|
s->divider = 0x0C;
|
|
s->mcr = UART_MCR_OUT2;
|
|
s->scr = 0;
|
|
s->tsr_retry = 0;
|
|
s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
|
|
s->poll_msl = 0;
|
|
|
|
s->timeout_ipending = 0;
|
|
timer_del(s->fifo_timeout_timer);
|
|
timer_del(s->modem_status_poll);
|
|
|
|
fifo8_reset(&s->recv_fifo);
|
|
fifo8_reset(&s->xmit_fifo);
|
|
|
|
s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
|
|
s->thr_ipending = 0;
|
|
s->last_break_enable = 0;
|
|
qemu_irq_lower(s->irq);
|
|
|
|
serial_update_msl(s);
|
|
s->msr &= ~UART_MSR_ANY_DELTA;
|
|
}
|
|
|
|
static int serial_be_change(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
|
|
qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
|
|
serial_event, serial_be_change, s, NULL, true);
|
|
|
|
serial_update_parameters(s);
|
|
|
|
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
|
|
&s->last_break_enable);
|
|
|
|
s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0;
|
|
serial_update_msl(s);
|
|
|
|
if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) {
|
|
serial_update_tiocm(s);
|
|
}
|
|
|
|
if (s->watch_tag > 0) {
|
|
g_source_remove(s->watch_tag);
|
|
s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
|
|
serial_watch_cb, s);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void serial_realize_core(SerialState *s, Error **errp)
|
|
{
|
|
s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
|
|
|
|
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
|
|
qemu_register_reset(serial_reset, s);
|
|
|
|
qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
|
|
serial_event, serial_be_change, s, NULL, true);
|
|
fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
|
|
fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
|
|
serial_reset(s);
|
|
}
|
|
|
|
void serial_exit_core(SerialState *s)
|
|
{
|
|
qemu_chr_fe_deinit(&s->chr, false);
|
|
|
|
timer_del(s->modem_status_poll);
|
|
timer_free(s->modem_status_poll);
|
|
|
|
timer_del(s->fifo_timeout_timer);
|
|
timer_free(s->fifo_timeout_timer);
|
|
|
|
fifo8_destroy(&s->recv_fifo);
|
|
fifo8_destroy(&s->xmit_fifo);
|
|
|
|
qemu_unregister_reset(serial_reset, s);
|
|
}
|
|
|
|
/* Change the main reference oscillator frequency. */
|
|
void serial_set_frequency(SerialState *s, uint32_t frequency)
|
|
{
|
|
s->baudbase = frequency;
|
|
serial_update_parameters(s);
|
|
}
|
|
|
|
const MemoryRegionOps serial_io_ops = {
|
|
.read = serial_ioport_read,
|
|
.write = serial_ioport_write,
|
|
.impl = {
|
|
.min_access_size = 1,
|
|
.max_access_size = 1,
|
|
},
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
|
|
Chardev *chr, MemoryRegion *system_io)
|
|
{
|
|
SerialState *s;
|
|
|
|
s = g_malloc0(sizeof(SerialState));
|
|
|
|
s->irq = irq;
|
|
s->baudbase = baudbase;
|
|
qemu_chr_fe_init(&s->chr, chr, &error_abort);
|
|
serial_realize_core(s, &error_fatal);
|
|
|
|
vmstate_register(NULL, base, &vmstate_serial, s);
|
|
|
|
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
|
|
memory_region_add_subregion(system_io, base, &s->io);
|
|
|
|
return s;
|
|
}
|
|
|
|
/* Memory mapped interface */
|
|
static uint64_t serial_mm_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
SerialState *s = opaque;
|
|
return serial_ioport_read(s, addr >> s->it_shift, 1);
|
|
}
|
|
|
|
static void serial_mm_write(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
SerialState *s = opaque;
|
|
value &= 255;
|
|
serial_ioport_write(s, addr >> s->it_shift, value, 1);
|
|
}
|
|
|
|
static const MemoryRegionOps serial_mm_ops[3] = {
|
|
[DEVICE_NATIVE_ENDIAN] = {
|
|
.read = serial_mm_read,
|
|
.write = serial_mm_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid.max_access_size = 8,
|
|
.impl.max_access_size = 8,
|
|
},
|
|
[DEVICE_LITTLE_ENDIAN] = {
|
|
.read = serial_mm_read,
|
|
.write = serial_mm_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid.max_access_size = 8,
|
|
.impl.max_access_size = 8,
|
|
},
|
|
[DEVICE_BIG_ENDIAN] = {
|
|
.read = serial_mm_read,
|
|
.write = serial_mm_write,
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
.valid.max_access_size = 8,
|
|
.impl.max_access_size = 8,
|
|
},
|
|
};
|
|
|
|
SerialState *serial_mm_init(MemoryRegion *address_space,
|
|
hwaddr base, int it_shift,
|
|
qemu_irq irq, int baudbase,
|
|
Chardev *chr, enum device_endian end)
|
|
{
|
|
SerialState *s;
|
|
|
|
s = g_malloc0(sizeof(SerialState));
|
|
|
|
s->it_shift = it_shift;
|
|
s->irq = irq;
|
|
s->baudbase = baudbase;
|
|
qemu_chr_fe_init(&s->chr, chr, &error_abort);
|
|
|
|
serial_realize_core(s, &error_fatal);
|
|
vmstate_register(NULL, base, &vmstate_serial, s);
|
|
|
|
memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
|
|
"serial", 8 << it_shift);
|
|
memory_region_add_subregion(address_space, base, &s->io);
|
|
return s;
|
|
}
|