220 lines
6.0 KiB
C
220 lines
6.0 KiB
C
#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "vga_int.h"
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#include "hw/virtio/virtio-pci.h"
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#include "qapi/error.h"
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/*
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* virtio-vga: This extends VirtioPCIProxy.
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*/
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#define TYPE_VIRTIO_VGA "virtio-vga"
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#define VIRTIO_VGA(obj) \
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OBJECT_CHECK(VirtIOVGA, (obj), TYPE_VIRTIO_VGA)
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typedef struct VirtIOVGA {
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VirtIOPCIProxy parent_obj;
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VirtIOGPU vdev;
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VGACommonState vga;
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MemoryRegion vga_mrs[3];
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} VirtIOVGA;
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static void virtio_vga_invalidate_display(void *opaque)
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{
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VirtIOVGA *vvga = opaque;
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if (vvga->vdev.enable) {
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virtio_gpu_ops.invalidate(&vvga->vdev);
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} else {
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vvga->vga.hw_ops->invalidate(&vvga->vga);
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}
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}
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static void virtio_vga_update_display(void *opaque)
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{
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VirtIOVGA *vvga = opaque;
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if (vvga->vdev.enable) {
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virtio_gpu_ops.gfx_update(&vvga->vdev);
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} else {
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vvga->vga.hw_ops->gfx_update(&vvga->vga);
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}
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}
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static void virtio_vga_text_update(void *opaque, console_ch_t *chardata)
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{
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VirtIOVGA *vvga = opaque;
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if (vvga->vdev.enable) {
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if (virtio_gpu_ops.text_update) {
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virtio_gpu_ops.text_update(&vvga->vdev, chardata);
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}
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} else {
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if (vvga->vga.hw_ops->text_update) {
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vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
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}
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}
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}
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static int virtio_vga_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
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{
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VirtIOVGA *vvga = opaque;
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if (virtio_gpu_ops.ui_info) {
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return virtio_gpu_ops.ui_info(&vvga->vdev, idx, info);
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}
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return -1;
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}
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static void virtio_vga_gl_block(void *opaque, bool block)
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{
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VirtIOVGA *vvga = opaque;
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if (virtio_gpu_ops.gl_block) {
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virtio_gpu_ops.gl_block(&vvga->vdev, block);
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}
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}
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static const GraphicHwOps virtio_vga_ops = {
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.invalidate = virtio_vga_invalidate_display,
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.gfx_update = virtio_vga_update_display,
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.text_update = virtio_vga_text_update,
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.ui_info = virtio_vga_ui_info,
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.gl_block = virtio_vga_gl_block,
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};
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static const VMStateDescription vmstate_virtio_vga = {
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.name = "virtio-vga",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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/* no pci stuff here, saving the virtio device will handle that */
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VMSTATE_STRUCT(vga, VirtIOVGA, 0, vmstate_vga_common, VGACommonState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* VGA device wrapper around PCI device around virtio GPU */
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static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
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{
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VirtIOVGA *vvga = VIRTIO_VGA(vpci_dev);
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VirtIOGPU *g = &vvga->vdev;
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VGACommonState *vga = &vvga->vga;
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Error *err = NULL;
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uint32_t offset;
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int i;
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/* init vga compat bits */
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vga->vram_size_mb = 8;
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vga_common_init(vga, OBJECT(vpci_dev), false);
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vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
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pci_address_space_io(&vpci_dev->pci_dev), true);
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pci_register_bar(&vpci_dev->pci_dev, 0,
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PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
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/*
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* Configure virtio bar and regions
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*
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* We use bar #2 for the mmio regions, to be compatible with stdvga.
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* virtio regions are moved to the end of bar #2, to make room for
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* the stdvga mmio registers at the start of bar #2.
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*/
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vpci_dev->modern_mem_bar_idx = 2;
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vpci_dev->msix_bar_idx = 4;
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if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
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/*
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* with page-per-vq=off there is no padding space we can use
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* for the stdvga registers. Make the common and isr regions
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* smaller then.
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*/
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vpci_dev->common.size /= 2;
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vpci_dev->isr.size /= 2;
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}
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offset = memory_region_size(&vpci_dev->modern_bar);
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offset -= vpci_dev->notify.size;
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vpci_dev->notify.offset = offset;
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offset -= vpci_dev->device.size;
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vpci_dev->device.offset = offset;
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offset -= vpci_dev->isr.size;
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vpci_dev->isr.offset = offset;
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offset -= vpci_dev->common.size;
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vpci_dev->common.offset = offset;
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/* init virtio bits */
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qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus));
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virtio_pci_force_virtio_1(vpci_dev);
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object_property_set_bool(OBJECT(g), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* add stdvga mmio regions */
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pci_std_vga_mmio_region_init(vga, &vpci_dev->modern_bar,
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vvga->vga_mrs, true);
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vga->con = g->scanout[0].con;
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graphic_console_set_hwops(vga->con, &virtio_vga_ops, vvga);
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for (i = 0; i < g->conf.max_outputs; i++) {
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object_property_set_link(OBJECT(g->scanout[i].con),
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OBJECT(vpci_dev),
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"device", errp);
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}
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}
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static void virtio_vga_reset(DeviceState *dev)
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{
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VirtIOVGA *vvga = VIRTIO_VGA(dev);
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vvga->vdev.enable = 0;
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vga_dirty_log_start(&vvga->vga);
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}
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static Property virtio_vga_properties[] = {
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DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void virtio_vga_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
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PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
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dc->props = virtio_vga_properties;
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dc->reset = virtio_vga_reset;
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dc->vmsd = &vmstate_virtio_vga;
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dc->hotpluggable = false;
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k->realize = virtio_vga_realize;
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pcidev_k->romfile = "vgabios-virtio.bin";
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pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
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}
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static void virtio_vga_inst_initfn(Object *obj)
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{
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VirtIOVGA *dev = VIRTIO_VGA(obj);
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virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
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TYPE_VIRTIO_GPU);
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}
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static TypeInfo virtio_vga_info = {
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.name = TYPE_VIRTIO_VGA,
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.parent = TYPE_VIRTIO_PCI,
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.instance_size = sizeof(struct VirtIOVGA),
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.instance_init = virtio_vga_inst_initfn,
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.class_init = virtio_vga_class_init,
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};
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static void virtio_vga_register_types(void)
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{
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type_register_static(&virtio_vga_info);
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}
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type_init(virtio_vga_register_types)
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