290 lines
8.3 KiB
C
290 lines
8.3 KiB
C
/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "target/ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target/ppc/mmu-hash64.h"
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#include "sysemu/numa.h"
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#include "sysemu/hw_accel.h"
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#include "qemu/error-report.h"
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static void spapr_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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target_ulong lpcr;
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cpu_reset(cs);
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/* Set compatibility mode to match the boot CPU, which was either set
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* by the machine reset code or by CAS. This should never fail.
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*/
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ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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lpcr = env->spr[SPR_LPCR];
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/* Set emulated LPCR to not send interrupts to hypervisor. Note that
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* under KVM, the actual HW LPCR will be set differently by KVM itself,
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* the settings below ensure proper operations with TCG in absence of
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* a real hypervisor.
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*
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* Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
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* real mode accesses, which thankfully defaults to 0 and isn't
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* accessible in guest mode.
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*
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* Disable Power-saving mode Exit Cause exceptions for the CPU, so
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* we don't get spurious wakups before an RTAS start-cpu call.
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*/
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lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
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lpcr |= LPCR_LPES0 | LPCR_LPES1;
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/* Set RMLS to the max (ie, 16G) */
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lpcr &= ~LPCR_RMLS;
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lpcr |= 1ull << LPCR_RMLS_SHIFT;
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ppc_store_lpcr(cpu, lpcr);
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/* Set a full AMOR so guest can use the AMR as it sees fit */
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env->spr[SPR_AMOR] = 0xffffffffffffffffull;
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}
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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env->nip = nip;
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env->gpr[3] = r3;
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CPU(cpu)->halted = 0;
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/* Enable Power-saving mode Exit Cause exceptions */
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ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
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}
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static void spapr_cpu_destroy(PowerPCCPU *cpu)
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{
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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}
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static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
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Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
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kvmppc_set_papr(cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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spapr_cpu_reset(cpu);
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}
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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const char *spapr_get_cpu_core_type(const char *cpu_type)
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{
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int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
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char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
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len, cpu_type);
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ObjectClass *oc = object_class_by_name(core_type);
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g_free(core_type);
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if (!oc) {
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return NULL;
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}
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return object_class_get_name(oc);
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}
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static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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Object *obj = OBJECT(sc->threads[i]);
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DeviceState *dev = DEVICE(obj);
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CPUState *cs = CPU(dev);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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spapr_cpu_destroy(cpu);
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object_unparent(cpu->intc);
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cpu_remove_sync(cs);
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object_unparent(obj);
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}
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g_free(sc->threads);
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}
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static void spapr_cpu_core_realize_child(Object *child,
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sPAPRMachineState *spapr, Error **errp)
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{
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Error *local_err = NULL;
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CPUState *cs = CPU(child);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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object_property_set_bool(child, true, "realized", &local_err);
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if (local_err) {
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goto error;
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}
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spapr_cpu_init(spapr, cpu, &local_err);
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if (local_err) {
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goto error;
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}
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cpu->intc = icp_create(child, spapr->icp_type, XICS_FABRIC(spapr),
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&local_err);
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if (local_err) {
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goto error;
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}
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return;
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error:
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error_propagate(errp, local_err);
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
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* tries to add a sPAPR CPU core to a non-pseries machine.
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*/
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sPAPRMachineState *spapr =
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(sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
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TYPE_SPAPR_MACHINE);
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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Error *local_err = NULL;
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Object *obj;
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int i, j;
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if (!spapr) {
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error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
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return;
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}
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sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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char id[32];
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CPUState *cs;
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PowerPCCPU *cpu;
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obj = object_new(scc->cpu_type);
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cs = CPU(obj);
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cpu = sc->threads[i] = POWERPC_CPU(obj);
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cs->cpu_index = cc->core_id + i;
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spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
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if (local_err) {
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goto err;
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}
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/* Set NUMA node for the threads belonged to core */
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cpu->node_id = sc->node_id;
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snprintf(id, sizeof(id), "thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj, &local_err);
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if (local_err) {
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goto err;
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}
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object_unref(obj);
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}
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for (j = 0; j < cc->nr_threads; j++) {
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obj = OBJECT(sc->threads[j]);
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spapr_cpu_core_realize_child(obj, spapr, &local_err);
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if (local_err) {
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goto err;
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}
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}
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return;
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err:
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while (--i >= 0) {
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obj = OBJECT(sc->threads[i]);
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object_unparent(obj);
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}
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g_free(sc->threads);
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error_propagate(errp, local_err);
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}
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static Property spapr_cpu_core_properties[] = {
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DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
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DEFINE_PROP_END_OF_LIST()
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};
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static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
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dc->realize = spapr_cpu_core_realize;
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dc->unrealize = spapr_cpu_core_unrealizefn;
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dc->props = spapr_cpu_core_properties;
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scc->cpu_type = data;
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}
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#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
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{ \
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.parent = TYPE_SPAPR_CPU_CORE, \
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.class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
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.class_init = spapr_cpu_core_class_init, \
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.name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo spapr_cpu_core_type_infos[] = {
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{
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.name = TYPE_SPAPR_CPU_CORE,
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.parent = TYPE_CPU_CORE,
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.abstract = true,
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.instance_size = sizeof(sPAPRCPUCore),
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.class_size = sizeof(sPAPRCPUCoreClass),
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},
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DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
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#ifdef CONFIG_KVM
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DEFINE_SPAPR_CPU_CORE_TYPE("host"),
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#endif
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};
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DEFINE_TYPES(spapr_cpu_core_type_infos)
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