ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
#ifndef HW_PCI_HOST_SABRE_H
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#define HW_PCI_HOST_SABRE_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/sparc/sun4u_iommu.h"
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#define MAX_IVEC 0x40
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/* OBIO IVEC IRQs */
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#define OBIO_HDD_IRQ 0x20
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#define OBIO_NIC_IRQ 0x21
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#define OBIO_LPT_IRQ 0x22
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#define OBIO_FDD_IRQ 0x27
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#define OBIO_KBD_IRQ 0x29
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#define OBIO_MSE_IRQ 0x2a
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#define OBIO_SER_IRQ 0x2b
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typedef struct SabrePCIState {
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PCIDevice parent_obj;
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} SabrePCIState;
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#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
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#define SABRE_PCI_DEVICE(obj) \
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OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
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typedef struct SabreState {
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PCIHostState parent_obj;
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hwaddr special_base;
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hwaddr mem_base;
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MemoryRegion sabre_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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IOMMUState *iommu;
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PCIBridge *bridgeA;
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PCIBridge *bridgeB;
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t pci_err_irq_map[4];
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uint32_t obio_irq_map[32];
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qemu_irq ivec_irqs[MAX_IVEC];
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unsigned int irq_request;
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uint32_t reset_control;
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unsigned int nr_resets;
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} SabreState;
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#define TYPE_SABRE "sabre"
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#define SABRE_DEVICE(obj) \
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OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
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#endif
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