OpenE2K/qemu-e2k
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qemu-e2k/include/hw/riscv
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Bernhard Beschow 9dfa6c2aec hw/riscv/sifive_e: Fix inheritance of SiFiveEState 
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
inherit from TYPE_MACHINE. This is an inconsistency which can cause
undefined behavior such as memory corruption.

Change SiFiveEState to inherit from MachineState since it is registered
as a machine.

Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220922075232.33653-1-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27 07:04:38 +10:00
..
boot_opensbi.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
boot.h hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() 2022-09-07 09:18:33 +02:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals 2022-09-07 09:18:33 +02:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h hw/riscv: opentitan: Expose the resetvec as a SoC property 2022-09-27 07:04:38 +10:00
riscv_hart.h Use OBJECT_DECLARE_SIMPLE_TYPE when possible 2020-09-18 14:12:32 -04:00
shakti_c.h Clean up header guards that don't match their file name 2022-05-11 16:49:06 +02:00
sifive_cpu.h
sifive_e.h hw/riscv/sifive_e: Fix inheritance of SiFiveEState 2022-09-27 07:04:38 +10:00
sifive_u.h hw/riscv: sifive_u: Use the PLIC config helper function 2021-10-28 14:39:23 +10:00
spike.h hw/riscv: spike: Allow using binary firmware as bios 2022-01-21 15:52:56 +10:00
virt.h hw/riscv: virt: fix the plic's address cells 2022-09-07 09:18:33 +02:00