qemu-e2k/tests/migration/aarch64/a-b-kernel.S
Thomas Huth c398c76187 tests/migration/aarch64: Speed up the aarch64 migration test
The migration tests spend a lot of time waiting for a sign of live
of the guest on the serial console. The aarch64 migration code only
outputs "B"s every couple of seconds (at least it takes more than 4
seconds between each characeter on my x86 laptop). There are a lot
of migration tests, and if each test that checks for a successful
migration waits for these characters before and after migration, the
wait time sums up to multiple minutes! Let's use a shorter delay to
speed things up.

While we're at it, also remove a superfluous masking with 0xff - we're
reading and storing bytes, so the upper bits of the register do not
matter anyway.

With these changes, the test runs twice as fast on my laptop, decreasing
the total run time from approx. 8 minutes to only 4 minutes!

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220819053802.296584-3-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220822165608.2980552-4-alex.bennee@linaro.org>
2022-08-24 10:14:49 +01:00

75 lines
1.8 KiB
ArmAsm

#
# Copyright (c) 2018 Red Hat, Inc. and/or its affiliates
#
# Author:
# Wei Huang <wei@redhat.com>
#
# This work is licensed under the terms of the GNU GPL, version 2 or later.
# See the COPYING file in the top-level directory.
#
# Note: Please make sure the compiler compiles the assembly code below with
# pc-relative address. Also the branch instructions should use relative
# addresses only.
#include "../migration-test.h"
.section .text
.globl _start
_start:
/* disable MMU to use phys mem address */
mrs x0, sctlr_el1
bic x0, x0, #(1<<0)
msr sctlr_el1, x0
isb
/* traverse test memory region */
mov x0, #ARM_TEST_MEM_START
mov x1, #ARM_TEST_MEM_END
/* output char 'A' to PL011 */
mov w3, 'A'
mov x2, #ARM_MACH_VIRT_UART
strb w3, [x2]
/* clean up memory */
mov w3, #0
mov x4, x0
clean:
strb w3, [x4]
add x4, x4, #TEST_MEM_PAGE_SIZE
cmp x4, x1
ble clean
/* w5 keeps a counter so we can limit the output speed */
mov w5, #0
/* main body */
mainloop:
mov x4, x0
innerloop:
/* increment the first byte of each page by 1 */
ldrb w3, [x4]
add w3, w3, #1
strb w3, [x4]
/* make sure QEMU user space can see consistent data as MMU is off */
dc civac, x4
add x4, x4, #TEST_MEM_PAGE_SIZE
cmp x4, x1
blt innerloop
add w5, w5, #1
and w5, w5, #0x1f
cmp w5, #0
bne mainloop
/* output char 'B' to PL011 */
mov w3, 'B'
strb w3, [x2]
b mainloop