Damien Hedde b636db306e hw/char/cadence_uart: add clock support ... Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-04-30 15:35:41 +01:00
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bcm2835_aux.c
cadence_uart.c	hw/char/cadence_uart: add clock support	2020-04-30 15:35:41 +01:00
cmsdk-apb-uart.c
debugcon.c
digic-uart.c
escc.c
etraxfs_ser.c
exynos4210_uart.c
grlib_apbuart.c
imx_serial.c
ipoctal232.c
Kconfig
lm32_juart.c
lm32_uart.c
Makefile.objs
mcf_uart.c
milkymist-uart.c
nrf51_uart.c
omap_uart.c
parallel-isa.c
parallel.c
pl011.c
sclpconsole-lm.c
sclpconsole.c
serial-isa.c
serial-pci-multi.c
serial-pci.c
serial.c	serial: Fix double migration data	2020-04-02 14:55:45 -04:00
sh_serial.c
spapr_vty.c
stm32f2xx_usart.c
terminal3270.c
trace-events	hw/char/cadence_uart: add clock support	2020-04-30 15:35:41 +01:00
virtio-console.c
virtio-serial-bus.c	virtio-serial-bus: Plug memory leak on realize() error paths	2020-03-29 06:33:47 -04:00
xen_console.c
xilinx_uartlite.c