Alistair Francis a8259b5323 riscv: Pass RISCVHartArrayState by pointer ... We were accidently passing RISCVHartArrayState by value instead of pointer. The type is 824 bytes long so let's correct that and pass it by pointer instead. Fixes: Coverity CID 1438099 Fixes: Coverity CID 1438100 Fixes: Coverity CID 1438101 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com		2021-01-16 14:34:46 -08:00
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boot.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
Kconfig	hw/riscv: microchip_pfsoc: Connect the SYSREG module	2020-11-03 07:17:23 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: add QSPI NOR flash	2020-12-17 21:56:43 -08:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	riscv/opentitan: Update the OpenTitan memory layout	2020-12-17 21:56:44 -08:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
sifive_u.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
spike.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
virt.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00