180 lines
5.6 KiB
C
180 lines
5.6 KiB
C
/*
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* IOAPIC emulation logic - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2009 Xiantao Zhang, Intel
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "monitor/monitor.h"
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#include "hw/i386/ioapic.h"
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#include "hw/i386/ioapic_internal.h"
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#include "hw/sysbus.h"
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/* ioapic_no count start from 0 to MAX_IOAPICS,
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* remove as static variable from ioapic_common_init.
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* now as a global variable, let child to increase the counter
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* then we can drop the 'instance_no' argument
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* and convert to our QOM's realize function
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*/
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int ioapic_no;
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static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap)
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{
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int i;
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monitor_printf(mon, "%-10s ", name);
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if (bitmap == 0) {
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monitor_printf(mon, "(none)\n");
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return;
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}
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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if (bitmap & (1 << i)) {
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monitor_printf(mon, "%-2u ", i);
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}
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}
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monitor_printf(mon, "\n");
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}
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void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s)
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{
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static const char *delm_str[] = {
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"fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"};
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uint32_t remote_irr = 0;
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int i;
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monitor_printf(mon, "ioapic id=0x%02x sel=0x%02x", s->id, s->ioregsel);
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if (s->ioregsel) {
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monitor_printf(mon, " (redir[%u])\n",
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(s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1);
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} else {
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monitor_printf(mon, "\n");
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}
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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uint64_t entry = s->ioredtbl[i];
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uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >>
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IOAPIC_LVT_DELIV_MODE_SHIFT);
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monitor_printf(mon, "pin %-2u 0x%016"PRIx64" dest=%"PRIx64
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" vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n",
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i, entry,
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(entry >> IOAPIC_LVT_DEST_SHIFT) &
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(entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf),
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entry & IOAPIC_VECTOR_MASK,
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entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi",
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entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge",
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entry & IOAPIC_LVT_MASKED ? "masked" : "",
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delm_str[delm],
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entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical");
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remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ?
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(entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0;
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}
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ioapic_irr_dump(mon, "IRR", s->irr);
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ioapic_irr_dump(mon, "Remote IRR", remote_irr);
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}
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void ioapic_reset_common(DeviceState *dev)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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int i;
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s->id = 0;
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s->ioregsel = 0;
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s->irr = 0;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
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}
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}
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static void ioapic_dispatch_pre_save(void *opaque)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(opaque);
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IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
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if (info->pre_save) {
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info->pre_save(s);
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}
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}
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static int ioapic_dispatch_post_load(void *opaque, int version_id)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(opaque);
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IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
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if (info->post_load) {
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info->post_load(s);
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}
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return 0;
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}
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static void ioapic_common_realize(DeviceState *dev, Error **errp)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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IOAPICCommonClass *info;
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if (ioapic_no >= MAX_IOAPICS) {
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error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS);
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return;
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}
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info = IOAPIC_COMMON_GET_CLASS(s);
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info->realize(dev, errp);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory);
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ioapic_no++;
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}
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static const VMStateDescription vmstate_ioapic_common = {
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.name = "ioapic",
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.version_id = 3,
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.minimum_version_id = 1,
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.pre_save = ioapic_dispatch_pre_save,
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.post_load = ioapic_dispatch_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(id, IOAPICCommonState),
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VMSTATE_UINT8(ioregsel, IOAPICCommonState),
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VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
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VMSTATE_UINT32_V(irr, IOAPICCommonState, 2),
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VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void ioapic_common_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = ioapic_common_realize;
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dc->vmsd = &vmstate_ioapic_common;
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}
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static const TypeInfo ioapic_common_type = {
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.name = TYPE_IOAPIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IOAPICCommonState),
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.class_size = sizeof(IOAPICCommonClass),
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.class_init = ioapic_common_class_init,
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.abstract = true,
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};
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static void ioapic_common_register_types(void)
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{
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type_register_static(&ioapic_common_type);
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}
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type_init(ioapic_common_register_types)
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