Peter Maydell c98d174c24 target-arm: Clear IT bits when taking exceptions in v7M ... When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2012-03-15 17:00:52 +00:00
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cpu.h	Rename CPUState -> CPUArchState	2012-03-14 22:20:27 +01:00
helper.c	target-arm: Clear IT bits when taking exceptions in v7M	2012-03-15 17:00:52 +00:00
helper.h	target-arm: Implement VFPv4 fused multiply-accumulate insns	2011-10-19 16:14:07 +00:00
iwmmxt_helper.c	target-arm: Don't overuse CPUState	2012-03-14 22:20:24 +01:00
machine.c	arm: Add dummy support for co-processor 15's secure config register	2012-01-13 17:25:08 +00:00
neon_helper.c	target-arm: Don't overuse CPUState	2012-03-14 22:20:24 +01:00
op_addsub.h	Correct spelling of licensed	2011-07-23 11:26:12 -05:00
op_helper.c	target-arm: Don't overuse CPUState	2012-03-14 22:20:24 +01:00
translate.c	target-arm: Don't overuse CPUState	2012-03-14 22:20:24 +01:00