Pawan Gupta 7fac38635e target/i386: Export TAA_NO bit to guests ... TSX Async Abort (TAA) is a side channel attack on internal buffers in some Intel processors similar to Microachitectural Data Sampling (MDS). Some future Intel processors will use the ARCH_CAP_TAA_NO bit in the IA32_ARCH_CAPABILITIES MSR to report that they are not vulnerable to TAA. Make this bit available to guests. Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-11-19 10:01:32 +01:00
..
alpha	target/alpha: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
arm	target/arm: Allow reading flags from FPSCR for M-profile	2019-11-01 20:41:00 +00:00
cris	cputlb: ensure _cmmu helper functions follow the naming standard	2019-10-28 15:12:38 +00:00
hppa	target/hppa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
i386	target/i386: Export TAA_NO bit to guests	2019-11-19 10:01:32 +01:00
lm32
m68k	target/m68k: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
microblaze	target/microblaze: Plug temp leak around eval_cond_jmp()	2019-11-12 16:35:26 +01:00
mips	target/mips: Refactor handling of vector compare 'less than' (signed) instructions	2019-10-25 18:37:01 +02:00
moxie
nios2
openrisc	target/openrisc: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
ppc	target/ppc: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
riscv	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4	target/sh4: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
sparc	target/sparc: Define an enumeration for accessing env->regwptr	2019-11-06 13:35:25 +01:00
tilegx
tricore
unicore32
xtensa	target/xtensa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00