130 lines
5.2 KiB
Diff
130 lines
5.2 KiB
Diff
From: Izik Eidus <izike@qumranet.com>
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add support to memory above the pci hole
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the new memory region is mapped after address 0x100000000,
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the bios take the size of the memory after the 0x100000000 from
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three new cmos bytes.
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diff --git a/bios/rombios.c b/bios/rombios.c
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index 1be0816..b70f249 100644
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--- a/bios/rombios.c
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+++ b/bios/rombios.c
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@@ -4442,22 +4442,25 @@ BX_DEBUG_INT15("case default:\n");
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#endif // BX_USE_PS2_MOUSE
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-void set_e820_range(ES, DI, start, end, type)
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+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
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Bit16u ES;
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Bit16u DI;
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Bit32u start;
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Bit32u end;
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+ Bit8u extra_start;
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+ Bit8u extra_end;
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Bit16u type;
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{
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write_word(ES, DI, start);
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write_word(ES, DI+2, start >> 16);
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- write_word(ES, DI+4, 0x00);
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+ write_word(ES, DI+4, extra_start);
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write_word(ES, DI+6, 0x00);
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end -= start;
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+ extra_end -= extra_start;
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write_word(ES, DI+8, end);
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write_word(ES, DI+10, end >> 16);
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- write_word(ES, DI+12, 0x0000);
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+ write_word(ES, DI+12, extra_end);
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write_word(ES, DI+14, 0x0000);
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write_word(ES, DI+16, type);
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@@ -4470,7 +4473,9 @@ int15_function32(regs, ES, DS, FLAGS)
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Bit16u ES, DS, FLAGS;
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{
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Bit32u extended_memory_size=0; // 64bits long
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+ Bit32u extra_lowbits_memory_size=0;
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Bit16u CX,DX;
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+ Bit8u extra_highbits_memory_size=0;
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BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
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@@ -4544,11 +4549,18 @@ ASM_END
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extended_memory_size += (1L * 1024 * 1024);
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}
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+ extra_lowbits_memory_size = inb_cmos(0x5c);
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+ extra_lowbits_memory_size <<= 8;
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+ extra_lowbits_memory_size |= inb_cmos(0x5b);
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+ extra_lowbits_memory_size *= 64;
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+ extra_lowbits_memory_size *= 1024;
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+ extra_highbits_memory_size = inb_cmos(0x5d);
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+
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switch(regs.u.r16.bx)
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{
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case 0:
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set_e820_range(ES, regs.u.r16.di,
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- 0x0000000L, 0x0009f000L, 1);
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+ 0x0000000L, 0x0009f000L, 0, 0, 1);
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regs.u.r32.ebx = 1;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4557,7 +4569,7 @@ ASM_END
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break;
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case 1:
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set_e820_range(ES, regs.u.r16.di,
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- 0x0009f000L, 0x000a0000L, 2);
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+ 0x0009f000L, 0x000a0000L, 0, 0, 2);
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regs.u.r32.ebx = 2;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4566,7 +4578,7 @@ ASM_END
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break;
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case 2:
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set_e820_range(ES, regs.u.r16.di,
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- 0x000e8000L, 0x00100000L, 2);
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+ 0x000e8000L, 0x00100000L, 0, 0, 2);
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regs.u.r32.ebx = 3;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4577,7 +4589,7 @@ ASM_END
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#if BX_ROMBIOS32
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set_e820_range(ES, regs.u.r16.di,
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0x00100000L,
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- extended_memory_size - ACPI_DATA_SIZE, 1);
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+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
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regs.u.r32.ebx = 4;
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#else
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set_e820_range(ES, regs.u.r16.di,
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@@ -4593,7 +4605,7 @@ ASM_END
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case 4:
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set_e820_range(ES, regs.u.r16.di,
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extended_memory_size - ACPI_DATA_SIZE,
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- extended_memory_size, 3); // ACPI RAM
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+ extended_memory_size ,0, 0, 3); // ACPI RAM
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regs.u.r32.ebx = 5;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4603,7 +4615,20 @@ ASM_END
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case 5:
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/* 256KB BIOS area at the end of 4 GB */
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set_e820_range(ES, regs.u.r16.di,
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- 0xfffc0000L, 0x00000000L, 2);
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+ 0xfffc0000L, 0x00000000L ,0, 0, 2);
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+ if (extra_highbits_memory_size || extra_lowbits_memory_size)
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+ regs.u.r32.ebx = 6;
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+ else
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+ regs.u.r32.ebx = 0;
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+ regs.u.r32.eax = 0x534D4150;
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+ regs.u.r32.ecx = 0x14;
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+ CLEAR_CF();
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+ return;
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+ case 6:
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+ /* Maping of memory above 4 GB */
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+ set_e820_range(ES, regs.u.r16.di, 0x00000000L,
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+ extra_lowbits_memory_size, 1, extra_highbits_memory_size
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+ + 1, 1);
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regs.u.r32.ebx = 0;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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