qemu-e2k/hw/intc
Stefan Hajnoczi cb6c406e26 First RISC-V PR for 8.2
* Remove 'host' CPU from TCG
  * riscv_htif Fixup printing on big endian hosts
  * Add zmmul isa string
  * Add smepmp isa string
  * Fix page_check_range use in fault-only-first
  * Use existing lookup tables for MixColumns
  * Add RISC-V vector cryptographic instruction set support
  * Implement WARL behaviour for mcountinhibit/mcounteren
  * Add Zihintntl extension ISA string to DTS
  * Fix zfa fleq.d and fltq.d
  * Fix upper/lower mtime write calculation
  * Make rtc variable names consistent
  * Use abi type for linux-user target_ucontext
  * Add RISC-V KVM AIA Support
  * Fix riscv,pmu DT node path in the virt machine
  * Update CSR bits name for svadu extension
  * Mark zicond non-experimental
  * Fix satp_mode_finalize() when satp_mode.supported = 0
  * Fix non-KVM --enable-debug build
  * Add new extensions to hwprobe
  * Use accelerated helper for AES64KS1I
  * Allocate itrigger timers only once
  * Respect mseccfg.RLB for pmpaddrX changes
  * Align the AIA model to v1.0 ratified spec
  * Don't read the CSR in riscv_csrrw_do64
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Merge tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.2

 * Remove 'host' CPU from TCG
 * riscv_htif Fixup printing on big endian hosts
 * Add zmmul isa string
 * Add smepmp isa string
 * Fix page_check_range use in fault-only-first
 * Use existing lookup tables for MixColumns
 * Add RISC-V vector cryptographic instruction set support
 * Implement WARL behaviour for mcountinhibit/mcounteren
 * Add Zihintntl extension ISA string to DTS
 * Fix zfa fleq.d and fltq.d
 * Fix upper/lower mtime write calculation
 * Make rtc variable names consistent
 * Use abi type for linux-user target_ucontext
 * Add RISC-V KVM AIA Support
 * Fix riscv,pmu DT node path in the virt machine
 * Update CSR bits name for svadu extension
 * Mark zicond non-experimental
 * Fix satp_mode_finalize() when satp_mode.supported = 0
 * Fix non-KVM --enable-debug build
 * Add new extensions to hwprobe
 * Use accelerated helper for AES64KS1I
 * Allocate itrigger timers only once
 * Respect mseccfg.RLB for pmpaddrX changes
 * Align the AIA model to v1.0 ratified spec
 * Don't read the CSR in riscv_csrrw_do64

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# gpg: Signature made Mon 11 Sep 2023 02:42:27 EDT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qemu: (45 commits)
  target/riscv: don't read CSR in riscv_csrrw_do64
  target/riscv: Align the AIA model to v1.0 ratified spec
  target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
  target/riscv: Allocate itrigger timers only once
  target/riscv: Use accelerated helper for AES64KS1I
  linux-user/riscv: Add new extensions to hwprobe
  hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
  hw/riscv/virt.c: fix non-KVM --enable-debug build
  riscv: zicond: make non-experimental
  target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
  target/riscv: Update CSR bits name for svadu extension
  hw/riscv: virt: Fix riscv,pmu DT node path
  target/riscv: select KVM AIA in riscv virt machine
  target/riscv: update APLIC and IMSIC to support KVM AIA
  target/riscv: Create an KVM AIA irqchip
  target/riscv: check the in-kernel irqchip support
  target/riscv: support the AIA device emulation with KVM enabled
  linux-user/riscv: Use abi type for target_ucontext
  hw/intc: Make rtc variable names consistent
  hw/intc: Fix upper/lower mtime write calculation
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-09-11 09:12:12 -04:00
..
allwinner-a10-pic.c hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 2023-06-19 11:24:21 +01:00
apic_common.c accel: Remove HAX accelerator 2023-08-31 19:46:43 +02:00
apic.c apic: disable reentrancy detection for apic-msi 2023-04-28 11:31:54 +02:00
arm_gic_common.c hw/intc/arm_gic: Rename 'first_cpu' argument 2023-06-28 14:27:59 +02:00
arm_gic_kvm.c
arm_gic.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
arm_gicv2m.c
arm_gicv3_common.c hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers 2023-06-28 14:27:59 +02:00
arm_gicv3_cpuif_common.c
arm_gicv3_cpuif.c
arm_gicv3_dist.c
arm_gicv3_its_common.c hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers 2023-06-28 14:27:59 +02:00
arm_gicv3_its_kvm.c
arm_gicv3_its.c hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte() 2023-09-08 16:41:34 +01:00
arm_gicv3_kvm.c
arm_gicv3_redist.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
arm_gicv3.c
armv7m_nvic.c arm: spelling fixes 2023-07-25 17:13:53 +03:00
aspeed_vic.c
bcm2835_ic.c
bcm2836_control.c
etraxfs_pic.c
exynos4210_combiner.c
exynos4210_gic.c
gic_internal.h
gicv3_internal.h
goldfish_pic.c
grlib_irqmp.c
heathrow_pic.c
i8259_common.c hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select 2023-03-08 00:37:48 +01:00
i8259.c hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select 2023-03-08 00:37:48 +01:00
imx_avic.c
imx_gpcv2.c
intc.c
ioapic_common.c
ioapic_internal.h
ioapic.c hw/intc/ioapic: Update KVM routes before redelivering IRQ, on RTE update 2023-03-15 11:52:25 +01:00
Kconfig s390x: Fix QEMU abort by selecting S390_FLIC_KVM 2023-07-18 09:36:27 +02:00
kvm_irqcount.c
loongarch_extioi.c bulk: Remove pointless QOM casts 2023-06-05 20:48:34 +02:00
loongarch_ipi.c hw/intc: Set physical cpuid route for LoongArch ipi device 2023-06-16 17:58:46 +08:00
loongarch_pch_msi.c
loongarch_pch_pic.c hw/intc/loongarch_pch: fix edge triggered irq handling 2023-08-24 11:17:59 +08:00
loongson_liointc.c
m68k_irqc.c
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
mips_gic.c
nios2_vic.c
omap_intc.c
ompic.c
openpic_kvm.c
openpic.c
pl190.c
pnv_xive2_regs.h pnv/xive2: Add definition for the ESB cache configuration register 2023-06-10 10:19:24 -03:00
pnv_xive2.c ppc/xive: Use address_space routines to access the machine RAM 2023-09-06 11:19:33 +02:00
pnv_xive_regs.h ppc/xive: Handle END triggers between chips with MMIOs 2023-09-06 11:19:33 +02:00
pnv_xive.c ppc/xive: Add support for the PC MMIOs 2023-09-06 11:19:33 +02:00
ppc-uic.c
realview_gic.c
riscv_aclint.c hw/intc: Make rtc variable names consistent 2023-09-11 11:45:55 +10:00
riscv_aplic.c hw/intc/riscv_aplic.c fix non-KVM --enable-debug build 2023-09-11 11:45:55 +10:00
riscv_imsic.c target/riscv: update APLIC and IMSIC to support KVM AIA 2023-09-11 11:45:55 +10:00
rx_icu.c
s390_flic_kvm.c s390x: spelling fixes 2023-07-25 17:13:45 +03:00
s390_flic.c
sh_intc.c
sifive_plic.c
slavio_intctl.c
spapr_xive_kvm.c
spapr_xive.c pnv/xive2: Add a get_config() method on the presenter class 2023-06-25 22:41:30 +02:00
trace-events pnv/xive: Print CPU target in all TIMA traces 2023-07-07 04:46:12 -03:00
trace.h
vgic_common.h
xics_kvm.c
xics_pnv.c
xics_spapr.c
xics.c
xilinx_intc.c
xive2.c pnv/xive: Allow mmio operations of any size on the ESB CI pages 2023-07-07 04:46:12 -03:00
xive.c ppc/xive: Introduce a new XiveRouter end_notify() handler 2023-09-06 11:19:33 +02:00
xlnx-pmu-iomod-intc.c
xlnx-zynqmp-ipi.c