8cefcc3b71
As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-11-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
91 lines
2.2 KiB
C
91 lines
2.2 KiB
C
/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMUV3_H
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#define HW_ARM_SMMUV3_H
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#include "hw/arm/smmu-common.h"
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#include "qom/object.h"
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#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
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typedef struct SMMUQueue {
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uint64_t base; /* base register */
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uint32_t prod;
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uint32_t cons;
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uint8_t entry_size;
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uint8_t log2size;
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} SMMUQueue;
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struct SMMUv3State {
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SMMUState smmu_state;
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uint32_t features;
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uint8_t sid_size;
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uint8_t sid_split;
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uint32_t idr[6];
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uint32_t iidr;
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uint32_t aidr;
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uint32_t cr[3];
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uint32_t cr0ack;
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uint32_t statusr;
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uint32_t gbpa;
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uint32_t irq_ctrl;
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uint32_t gerror;
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uint32_t gerrorn;
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uint64_t gerror_irq_cfg0;
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uint32_t gerror_irq_cfg1;
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uint32_t gerror_irq_cfg2;
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uint64_t strtab_base;
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uint32_t strtab_base_cfg;
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uint64_t eventq_irq_cfg0;
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uint32_t eventq_irq_cfg1;
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uint32_t eventq_irq_cfg2;
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SMMUQueue eventq, cmdq;
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qemu_irq irq[4];
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QemuMutex mutex;
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char *stage;
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};
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typedef enum {
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SMMU_IRQ_EVTQ,
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SMMU_IRQ_PRIQ,
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SMMU_IRQ_CMD_SYNC,
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SMMU_IRQ_GERROR,
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} SMMUIrq;
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struct SMMUv3Class {
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/*< private >*/
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SMMUBaseClass smmu_base_class;
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/*< public >*/
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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#define TYPE_ARM_SMMUV3 "arm-smmuv3"
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OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
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#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P)
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#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P)
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#endif
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