72d680e408
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
#ifndef QEMU_MIPS_DEFS_H
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#define QEMU_MIPS_DEFS_H
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/* Real pages are variable size... */
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#define MIPS_TLB_MAX 128
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/*
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* bit definitions for insn_flags (ISAs/ASEs flags)
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* ------------------------------------------------
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*/
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/*
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* bits 0-23: MIPS base instruction sets
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*/
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#define ISA_MIPS1 0x0000000000000001ULL
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#define ISA_MIPS2 0x0000000000000002ULL
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#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
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#define ISA_MIPS4 0x0000000000000008ULL
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#define ISA_MIPS5 0x0000000000000010ULL
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#define ISA_MIPS_R1 0x0000000000000020ULL
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#define ISA_MIPS_R2 0x0000000000000040ULL
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#define ISA_MIPS_R3 0x0000000000000080ULL
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#define ISA_MIPS_R5 0x0000000000000100ULL
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#define ISA_MIPS_R6 0x0000000000000200ULL
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#define ISA_NANOMIPS32 0x0000000000008000ULL
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/*
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* bits 24-39: MIPS ASEs
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*/
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#define ASE_MIPS16 0x0000000001000000ULL
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#define ASE_MIPS3D 0x0000000002000000ULL
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#define ASE_MDMX 0x0000000004000000ULL
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#define ASE_DSP 0x0000000008000000ULL
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#define ASE_DSP_R2 0x0000000010000000ULL
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#define ASE_DSP_R3 0x0000000020000000ULL
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#define ASE_MT 0x0000000040000000ULL
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#define ASE_SMARTMIPS 0x0000000080000000ULL
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#define ASE_MICROMIPS 0x0000000100000000ULL
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/*
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* bits 40-51: vendor-specific base instruction sets
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*/
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#define INSN_VR54XX 0x0000010000000000ULL
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#define INSN_R5900 0x0000020000000000ULL
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#define INSN_LOONGSON2E 0x0000040000000000ULL
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#define INSN_LOONGSON2F 0x0000080000000000ULL
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#define INSN_LOONGSON3A 0x0000100000000000ULL
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#define INSN_OCTEON 0x0000200000000000ULL
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/*
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* bits 52-63: vendor-specific ASEs
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*/
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/* MultiMedia Instructions defined by R5900 */
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#define ASE_MMI 0x0010000000000000ULL
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/* MIPS eXtension/enhanced Unit defined by Ingenic */
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#define ASE_MXU 0x0020000000000000ULL
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/* Loongson MultiMedia Instructions */
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#define ASE_LMMI 0x0040000000000000ULL
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/* Loongson EXTensions */
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#define ASE_LEXT 0x0080000000000000ULL
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/* MIPS CPU defines. */
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#define CPU_MIPS1 (ISA_MIPS1)
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#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
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#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
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#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
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#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
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#define CPU_MIPS64 (ISA_MIPS3)
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/* MIPS Technologies "Release 1" */
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#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
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#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
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/* MIPS Technologies "Release 2" */
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#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
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#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
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/* MIPS Technologies "Release 3" */
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#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
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#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
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/* MIPS Technologies "Release 5" */
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#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
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#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
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/* MIPS Technologies "Release 6" */
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#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
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#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
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/*
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* Strictly follow the architecture standard:
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* - Disallow "special" instruction handling for PMON/SPIM.
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* Note that we still maintain Count/Compare to match the host clock.
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*
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* #define MIPS_STRICT_STANDARD 1
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*/
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#endif /* QEMU_MIPS_DEFS_H */
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