cd419bc63d
Do as little work as possible within the macro. Split out helper functions and pass in arguments instead. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1023 lines
32 KiB
C
1023 lines
32 KiB
C
/*
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* Altera Nios II emulation for qemu: main translation routines.
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*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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* Copyright (C) 2012 Chris Wulff <crwulff@gmail.com>
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* Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
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* (Portions of this file that were originally from nios2sim-ng.)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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#include "exec/exec-all.h"
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#include "disas/disas.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/log.h"
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#include "exec/cpu_ldst.h"
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#include "exec/translator.h"
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#include "qemu/qemu-print.h"
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#include "exec/gen-icount.h"
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#include "semihosting/semihost.h"
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
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#define INSTRUCTION_FLG(func, flags) { (func), (flags) }
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#define INSTRUCTION(func) \
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INSTRUCTION_FLG(func, 0)
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#define INSTRUCTION_NOP() \
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INSTRUCTION_FLG(nop, 0)
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#define INSTRUCTION_UNIMPLEMENTED() \
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INSTRUCTION_FLG(gen_excp, EXCP_UNIMPL)
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#define INSTRUCTION_ILLEGAL() \
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INSTRUCTION_FLG(gen_excp, EXCP_ILLEGAL)
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/* Special R-Type instruction opcode */
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#define INSN_R_TYPE 0x3A
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/* I-Type instruction parsing */
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typedef struct {
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uint8_t op;
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union {
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uint16_t u;
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int16_t s;
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} imm16;
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uint8_t b;
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uint8_t a;
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} InstrIType;
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#define I_TYPE(instr, code) \
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InstrIType (instr) = { \
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.op = extract32((code), 0, 6), \
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.imm16.u = extract32((code), 6, 16), \
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.b = extract32((code), 22, 5), \
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.a = extract32((code), 27, 5), \
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}
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typedef target_ulong ImmFromIType(const InstrIType *);
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static target_ulong imm_unsigned(const InstrIType *i)
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{
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return i->imm16.u;
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}
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static target_ulong imm_signed(const InstrIType *i)
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{
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return i->imm16.s;
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}
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static target_ulong imm_shifted(const InstrIType *i)
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{
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return i->imm16.u << 16;
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}
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/* R-Type instruction parsing */
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typedef struct {
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uint8_t op;
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uint8_t imm5;
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uint8_t opx;
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uint8_t c;
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uint8_t b;
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uint8_t a;
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} InstrRType;
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#define R_TYPE(instr, code) \
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InstrRType (instr) = { \
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.op = extract32((code), 0, 6), \
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.imm5 = extract32((code), 6, 5), \
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.opx = extract32((code), 11, 6), \
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.c = extract32((code), 17, 5), \
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.b = extract32((code), 22, 5), \
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.a = extract32((code), 27, 5), \
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}
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/* J-Type instruction parsing */
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typedef struct {
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uint8_t op;
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uint32_t imm26;
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} InstrJType;
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#define J_TYPE(instr, code) \
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InstrJType (instr) = { \
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.op = extract32((code), 0, 6), \
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.imm26 = extract32((code), 6, 26), \
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}
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typedef void GenFn2i(TCGv, TCGv, target_long);
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong pc;
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int mem_idx;
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const ControlRegState *cr_state;
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} DisasContext;
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static TCGv cpu_R[NUM_GP_REGS];
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static TCGv cpu_pc;
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typedef struct Nios2Instruction {
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void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags);
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uint32_t flags;
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} Nios2Instruction;
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static uint8_t get_opcode(uint32_t code)
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{
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I_TYPE(instr, code);
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return instr.op;
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}
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static uint8_t get_opxcode(uint32_t code)
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{
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R_TYPE(instr, code);
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return instr.opx;
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}
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static TCGv load_gpr(DisasContext *dc, unsigned reg)
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{
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assert(reg < NUM_GP_REGS);
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if (unlikely(reg == R_ZERO)) {
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return tcg_constant_tl(0);
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}
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return cpu_R[reg];
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}
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static void t_gen_helper_raise_exception(DisasContext *dc,
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uint32_t index)
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{
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tcg_gen_movi_tl(cpu_pc, dc->pc);
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gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
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dc->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest)
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{
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const TranslationBlock *tb = dc->base.tb;
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if (translator_use_goto_tb(&dc->base, dest)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_exit_tb(tb, n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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t_gen_helper_raise_exception(dc, flags);
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}
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static bool gen_check_supervisor(DisasContext *dc)
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{
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if (dc->base.tb->flags & CR_STATUS_U) {
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/* CPU in user mode, privileged instruction called, stop. */
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t_gen_helper_raise_exception(dc, EXCP_SUPERI);
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return false;
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}
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return true;
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}
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/*
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* Used as a placeholder for all instructions which do not have
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* an effect on the simulator (e.g. flush, sync)
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*/
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static void nop(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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/* Nothing to do here */
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}
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/*
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* J-Type instructions
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*/
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static void jmpi(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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J_TYPE(instr, code);
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gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2));
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dc->base.is_jmp = DISAS_NORETURN;
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}
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static void call(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
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jmpi(dc, code, flags);
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}
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/*
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* I-Type instructions
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*/
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/* Load instructions */
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static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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I_TYPE(instr, code);
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TCGv addr = tcg_temp_new();
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TCGv data;
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/*
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* WARNING: Loads into R_ZERO are ignored, but we must generate the
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* memory access itself to emulate the CPU precisely. Load
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* from a protected page to R_ZERO will cause SIGSEGV on
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* the Nios2 CPU.
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*/
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if (likely(instr.b != R_ZERO)) {
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data = cpu_R[instr.b];
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} else {
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data = tcg_temp_new();
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}
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tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
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tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
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if (unlikely(instr.b == R_ZERO)) {
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tcg_temp_free(data);
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}
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tcg_temp_free(addr);
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}
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/* Store instructions */
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static void gen_stx(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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I_TYPE(instr, code);
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TCGv val = load_gpr(dc, instr.b);
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TCGv addr = tcg_temp_new();
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tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
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tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags);
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tcg_temp_free(addr);
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}
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/* Branch instructions */
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static void br(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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I_TYPE(instr, code);
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gen_goto_tb(dc, 0, dc->base.pc_next + (instr.imm16.s & -4));
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dc->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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I_TYPE(instr, code);
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TCGLabel *l1 = gen_new_label();
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tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1);
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gen_goto_tb(dc, 0, dc->base.pc_next);
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gen_set_label(l1);
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gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4));
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dc->base.is_jmp = DISAS_NORETURN;
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}
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/* Comparison instructions */
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static void do_i_cmpxx(DisasContext *dc, uint32_t insn,
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TCGCond cond, ImmFromIType *imm)
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{
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I_TYPE(instr, insn);
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if (likely(instr.b != R_ZERO)) {
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tcg_gen_setcondi_tl(cond, cpu_R[instr.b],
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load_gpr(dc, instr.a), imm(&instr));
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}
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}
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#define gen_i_cmpxx(fname, imm) \
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static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
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{ do_i_cmpxx(dc, code, flags, imm); }
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gen_i_cmpxx(gen_cmpxxsi, imm_signed)
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gen_i_cmpxx(gen_cmpxxui, imm_unsigned)
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/* Math/logic instructions */
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static void do_i_math_logic(DisasContext *dc, uint32_t insn,
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GenFn2i *fn, ImmFromIType *imm,
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bool x_op_0_eq_x)
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{
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I_TYPE(instr, insn);
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target_ulong val;
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if (unlikely(instr.b == R_ZERO)) {
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/* Store to R_ZERO is ignored -- this catches the canonical NOP. */
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return;
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}
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val = imm(&instr);
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if (instr.a == R_ZERO) {
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/* This catches the canonical expansions of movi and movhi. */
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tcg_gen_movi_tl(cpu_R[instr.b], x_op_0_eq_x ? val : 0);
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} else {
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fn(cpu_R[instr.b], cpu_R[instr.a], val);
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}
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}
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#define gen_i_math_logic(fname, insn, x_op_0, imm) \
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static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
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{ do_i_math_logic(dc, code, tcg_gen_##insn##_tl, imm, x_op_0); }
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gen_i_math_logic(addi, addi, 1, imm_signed)
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gen_i_math_logic(muli, muli, 0, imm_signed)
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gen_i_math_logic(andi, andi, 0, imm_unsigned)
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gen_i_math_logic(ori, ori, 1, imm_unsigned)
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gen_i_math_logic(xori, xori, 1, imm_unsigned)
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gen_i_math_logic(andhi, andi, 0, imm_shifted)
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gen_i_math_logic(orhi , ori, 1, imm_shifted)
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gen_i_math_logic(xorhi, xori, 1, imm_shifted)
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/* Prototype only, defined below */
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static void handle_r_type_instr(DisasContext *dc, uint32_t code,
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uint32_t flags);
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static const Nios2Instruction i_type_instructions[] = {
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INSTRUCTION(call), /* call */
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INSTRUCTION(jmpi), /* jmpi */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_ldx, MO_UB), /* ldbu */
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INSTRUCTION(addi), /* addi */
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INSTRUCTION_FLG(gen_stx, MO_UB), /* stb */
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INSTRUCTION(br), /* br */
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INSTRUCTION_FLG(gen_ldx, MO_SB), /* ldb */
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INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_GE), /* cmpgei */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhu */
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INSTRUCTION(andi), /* andi */
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INSTRUCTION_FLG(gen_stx, MO_UW), /* sth */
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INSTRUCTION_FLG(gen_bxx, TCG_COND_GE), /* bge */
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INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldh */
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INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_LT), /* cmplti */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_NOP(), /* initda */
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INSTRUCTION(ori), /* ori */
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INSTRUCTION_FLG(gen_stx, MO_UL), /* stw */
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INSTRUCTION_FLG(gen_bxx, TCG_COND_LT), /* blt */
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INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldw */
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INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_NE), /* cmpnei */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_NOP(), /* flushda */
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INSTRUCTION(xori), /* xori */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_bxx, TCG_COND_NE), /* bne */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_cmpxxsi, TCG_COND_EQ), /* cmpeqi */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_ldx, MO_UB), /* ldbuio */
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INSTRUCTION(muli), /* muli */
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INSTRUCTION_FLG(gen_stx, MO_UB), /* stbio */
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INSTRUCTION_FLG(gen_bxx, TCG_COND_EQ), /* beq */
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INSTRUCTION_FLG(gen_ldx, MO_SB), /* ldbio */
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INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_GEU), /* cmpgeui */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(gen_ldx, MO_UW), /* ldhuio */
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INSTRUCTION(andhi), /* andhi */
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INSTRUCTION_FLG(gen_stx, MO_UW), /* sthio */
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INSTRUCTION_FLG(gen_bxx, TCG_COND_GEU), /* bgeu */
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INSTRUCTION_FLG(gen_ldx, MO_SW), /* ldhio */
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INSTRUCTION_FLG(gen_cmpxxui, TCG_COND_LTU), /* cmpltui */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_UNIMPLEMENTED(), /* custom */
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INSTRUCTION_NOP(), /* initd */
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INSTRUCTION(orhi), /* orhi */
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INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */
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INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */
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INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */
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INSTRUCTION_UNIMPLEMENTED(), /* rdprs */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */
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INSTRUCTION_NOP(), /* flushd */
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INSTRUCTION(xorhi), /* xorhi */
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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INSTRUCTION_ILLEGAL(),
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};
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/*
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* R-Type instructions
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*/
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/*
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* status <- estatus
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* PC <- ea
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*/
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static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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if (!gen_check_supervisor(dc)) {
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return;
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}
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#ifdef CONFIG_USER_ONLY
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g_assert_not_reached();
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#else
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TCGv tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
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gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
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tcg_temp_free(tmp);
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dc->base.is_jmp = DISAS_NORETURN;
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#endif
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}
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/* PC <- ra */
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static void ret(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]);
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dc->base.is_jmp = DISAS_JUMP;
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}
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/*
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* status <- bstatus
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* PC <- ba
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*/
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static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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if (!gen_check_supervisor(dc)) {
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return;
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}
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#ifdef CONFIG_USER_ONLY
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g_assert_not_reached();
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#else
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TCGv tmp = tcg_temp_new();
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
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gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
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tcg_temp_free(tmp);
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|
|
dc->base.is_jmp = DISAS_NORETURN;
|
|
#endif
|
|
}
|
|
|
|
/* PC <- rA */
|
|
static void jmp(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, code);
|
|
|
|
tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
|
|
|
|
dc->base.is_jmp = DISAS_JUMP;
|
|
}
|
|
|
|
/* rC <- PC + 4 */
|
|
static void nextpc(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, code);
|
|
|
|
if (likely(instr.c != R_ZERO)) {
|
|
tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ra <- PC + 4
|
|
* PC <- rA
|
|
*/
|
|
static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, code);
|
|
|
|
tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a));
|
|
tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next);
|
|
|
|
dc->base.is_jmp = DISAS_JUMP;
|
|
}
|
|
|
|
/* rC <- ctlN */
|
|
static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
if (!gen_check_supervisor(dc)) {
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
g_assert_not_reached();
|
|
#else
|
|
R_TYPE(instr, code);
|
|
TCGv t1, t2;
|
|
|
|
if (unlikely(instr.c == R_ZERO)) {
|
|
return;
|
|
}
|
|
|
|
/* Reserved registers read as zero. */
|
|
if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) {
|
|
tcg_gen_movi_tl(cpu_R[instr.c], 0);
|
|
return;
|
|
}
|
|
|
|
switch (instr.imm5) {
|
|
case CR_IPENDING:
|
|
/*
|
|
* The value of the ipending register is synthetic.
|
|
* In hw, this is the AND of a set of hardware irq lines
|
|
* with the ienable register. In qemu, we re-use the space
|
|
* of CR_IPENDING to store the set of irq lines, and so we
|
|
* must perform the AND here, and anywhere else we need the
|
|
* guest value of ipending.
|
|
*/
|
|
t1 = tcg_temp_new();
|
|
t2 = tcg_temp_new();
|
|
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
|
|
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
|
|
tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
|
|
tcg_temp_free(t1);
|
|
tcg_temp_free(t2);
|
|
break;
|
|
default:
|
|
tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
|
|
offsetof(CPUNios2State, ctrl[instr.imm5]));
|
|
break;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* ctlN <- rA */
|
|
static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
if (!gen_check_supervisor(dc)) {
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
g_assert_not_reached();
|
|
#else
|
|
R_TYPE(instr, code);
|
|
TCGv v = load_gpr(dc, instr.a);
|
|
uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]);
|
|
uint32_t wr = dc->cr_state[instr.imm5].writable;
|
|
uint32_t ro = dc->cr_state[instr.imm5].readonly;
|
|
|
|
/* Skip reserved or readonly registers. */
|
|
if (wr == 0) {
|
|
return;
|
|
}
|
|
|
|
switch (instr.imm5) {
|
|
case CR_PTEADDR:
|
|
gen_helper_mmu_write_pteaddr(cpu_env, v);
|
|
break;
|
|
case CR_TLBACC:
|
|
gen_helper_mmu_write_tlbacc(cpu_env, v);
|
|
break;
|
|
case CR_TLBMISC:
|
|
gen_helper_mmu_write_tlbmisc(cpu_env, v);
|
|
break;
|
|
case CR_STATUS:
|
|
case CR_IENABLE:
|
|
/* If interrupts were enabled using WRCTL, trigger them. */
|
|
dc->base.is_jmp = DISAS_UPDATE;
|
|
/* fall through */
|
|
default:
|
|
if (wr == -1) {
|
|
/* The register is entirely writable. */
|
|
tcg_gen_st_tl(v, cpu_env, ofs);
|
|
} else {
|
|
/*
|
|
* The register is partially read-only or reserved:
|
|
* merge the value.
|
|
*/
|
|
TCGv n = tcg_temp_new();
|
|
|
|
tcg_gen_andi_tl(n, v, wr);
|
|
|
|
if (ro != 0) {
|
|
TCGv o = tcg_temp_new();
|
|
tcg_gen_ld_tl(o, cpu_env, ofs);
|
|
tcg_gen_andi_tl(o, o, ro);
|
|
tcg_gen_or_tl(n, n, o);
|
|
tcg_temp_free(o);
|
|
}
|
|
|
|
tcg_gen_st_tl(n, cpu_env, ofs);
|
|
tcg_temp_free(n);
|
|
}
|
|
break;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* Comparison instructions */
|
|
static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, code);
|
|
if (likely(instr.c != R_ZERO)) {
|
|
tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a],
|
|
cpu_R[instr.b]);
|
|
}
|
|
}
|
|
|
|
/* Math/logic instructions */
|
|
#define gen_r_math_logic(fname, insn, op3) \
|
|
static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
|
|
{ \
|
|
R_TYPE(instr, (code)); \
|
|
if (likely(instr.c != R_ZERO)) { \
|
|
tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); \
|
|
} \
|
|
}
|
|
|
|
gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b))
|
|
gen_r_math_logic(sub, sub_tl, load_gpr(dc, instr.b))
|
|
gen_r_math_logic(mul, mul_tl, load_gpr(dc, instr.b))
|
|
|
|
gen_r_math_logic(and, and_tl, load_gpr(dc, instr.b))
|
|
gen_r_math_logic(or, or_tl, load_gpr(dc, instr.b))
|
|
gen_r_math_logic(xor, xor_tl, load_gpr(dc, instr.b))
|
|
gen_r_math_logic(nor, nor_tl, load_gpr(dc, instr.b))
|
|
|
|
gen_r_math_logic(srai, sari_tl, instr.imm5)
|
|
gen_r_math_logic(srli, shri_tl, instr.imm5)
|
|
gen_r_math_logic(slli, shli_tl, instr.imm5)
|
|
gen_r_math_logic(roli, rotli_tl, instr.imm5)
|
|
|
|
#define gen_r_mul(fname, insn) \
|
|
static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
|
|
{ \
|
|
R_TYPE(instr, (code)); \
|
|
if (likely(instr.c != R_ZERO)) { \
|
|
TCGv t0 = tcg_temp_new(); \
|
|
tcg_gen_##insn(t0, cpu_R[instr.c], \
|
|
load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \
|
|
tcg_temp_free(t0); \
|
|
} \
|
|
}
|
|
|
|
gen_r_mul(mulxss, muls2_tl)
|
|
gen_r_mul(mulxuu, mulu2_tl)
|
|
gen_r_mul(mulxsu, mulsu2_tl)
|
|
|
|
#define gen_r_shift_s(fname, insn) \
|
|
static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
|
|
{ \
|
|
R_TYPE(instr, (code)); \
|
|
if (likely(instr.c != R_ZERO)) { \
|
|
TCGv t0 = tcg_temp_new(); \
|
|
tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); \
|
|
tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); \
|
|
tcg_temp_free(t0); \
|
|
} \
|
|
}
|
|
|
|
gen_r_shift_s(sra, sar_tl)
|
|
gen_r_shift_s(srl, shr_tl)
|
|
gen_r_shift_s(sll, shl_tl)
|
|
gen_r_shift_s(rol, rotl_tl)
|
|
gen_r_shift_s(ror, rotr_tl)
|
|
|
|
static void divs(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, (code));
|
|
TCGv dest;
|
|
|
|
if (instr.c == R_ZERO) {
|
|
dest = tcg_temp_new();
|
|
} else {
|
|
dest = cpu_R[instr.c];
|
|
}
|
|
|
|
gen_helper_divs(dest, cpu_env,
|
|
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
|
|
|
|
if (instr.c == R_ZERO) {
|
|
tcg_temp_free(dest);
|
|
}
|
|
}
|
|
|
|
static void divu(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
R_TYPE(instr, (code));
|
|
TCGv dest;
|
|
|
|
if (instr.c == R_ZERO) {
|
|
dest = tcg_temp_new();
|
|
} else {
|
|
dest = cpu_R[instr.c];
|
|
}
|
|
|
|
gen_helper_divu(dest, cpu_env,
|
|
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
|
|
|
|
if (instr.c == R_ZERO) {
|
|
tcg_temp_free(dest);
|
|
}
|
|
}
|
|
|
|
static void trap(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
/*
|
|
* The imm5 field is not stored anywhere on real hw; the kernel
|
|
* has to load the insn and extract the field. But we can make
|
|
* things easier for cpu_loop if we pop this into env->error_code.
|
|
*/
|
|
R_TYPE(instr, code);
|
|
tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env,
|
|
offsetof(CPUNios2State, error_code));
|
|
#endif
|
|
t_gen_helper_raise_exception(dc, EXCP_TRAP);
|
|
}
|
|
|
|
static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
#ifndef CONFIG_USER_ONLY
|
|
/* The semihosting instruction is "break 1". */
|
|
R_TYPE(instr, code);
|
|
if (semihosting_enabled() && instr.imm5 == 1) {
|
|
t_gen_helper_raise_exception(dc, EXCP_SEMIHOST);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
t_gen_helper_raise_exception(dc, EXCP_BREAK);
|
|
}
|
|
|
|
static const Nios2Instruction r_type_instructions[] = {
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(eret), /* eret */
|
|
INSTRUCTION(roli), /* roli */
|
|
INSTRUCTION(rol), /* rol */
|
|
INSTRUCTION_NOP(), /* flushp */
|
|
INSTRUCTION(ret), /* ret */
|
|
INSTRUCTION(nor), /* nor */
|
|
INSTRUCTION(mulxuu), /* mulxuu */
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_GE), /* cmpge */
|
|
INSTRUCTION(bret), /* bret */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(ror), /* ror */
|
|
INSTRUCTION_NOP(), /* flushi */
|
|
INSTRUCTION(jmp), /* jmp */
|
|
INSTRUCTION(and), /* and */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_LT), /* cmplt */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(slli), /* slli */
|
|
INSTRUCTION(sll), /* sll */
|
|
INSTRUCTION_UNIMPLEMENTED(), /* wrprs */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(or), /* or */
|
|
INSTRUCTION(mulxsu), /* mulxsu */
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_NE), /* cmpne */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(srli), /* srli */
|
|
INSTRUCTION(srl), /* srl */
|
|
INSTRUCTION(nextpc), /* nextpc */
|
|
INSTRUCTION(callr), /* callr */
|
|
INSTRUCTION(xor), /* xor */
|
|
INSTRUCTION(mulxss), /* mulxss */
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_EQ), /* cmpeq */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(divu), /* divu */
|
|
INSTRUCTION(divs), /* div */
|
|
INSTRUCTION(rdctl), /* rdctl */
|
|
INSTRUCTION(mul), /* mul */
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_GEU), /* cmpgeu */
|
|
INSTRUCTION_NOP(), /* initi */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(trap), /* trap */
|
|
INSTRUCTION(wrctl), /* wrctl */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_FLG(gen_cmpxx, TCG_COND_LTU), /* cmpltu */
|
|
INSTRUCTION(add), /* add */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(gen_break), /* break */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(nop), /* nop */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION(sub), /* sub */
|
|
INSTRUCTION(srai), /* srai */
|
|
INSTRUCTION(sra), /* sra */
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
INSTRUCTION_ILLEGAL(),
|
|
};
|
|
|
|
static void handle_r_type_instr(DisasContext *dc, uint32_t code, uint32_t flags)
|
|
{
|
|
uint8_t opx;
|
|
const Nios2Instruction *instr;
|
|
|
|
opx = get_opxcode(code);
|
|
if (unlikely(opx >= ARRAY_SIZE(r_type_instructions))) {
|
|
goto illegal_op;
|
|
}
|
|
|
|
instr = &r_type_instructions[opx];
|
|
instr->handler(dc, code, instr->flags);
|
|
|
|
return;
|
|
|
|
illegal_op:
|
|
t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
|
|
}
|
|
|
|
static const char * const gr_regnames[NUM_GP_REGS] = {
|
|
"zero", "at", "r2", "r3",
|
|
"r4", "r5", "r6", "r7",
|
|
"r8", "r9", "r10", "r11",
|
|
"r12", "r13", "r14", "r15",
|
|
"r16", "r17", "r18", "r19",
|
|
"r20", "r21", "r22", "r23",
|
|
"et", "bt", "gp", "sp",
|
|
"fp", "ea", "ba", "ra",
|
|
};
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
static const char * const cr_regnames[NUM_CR_REGS] = {
|
|
"status", "estatus", "bstatus", "ienable",
|
|
"ipending", "cpuid", "res6", "exception",
|
|
"pteaddr", "tlbacc", "tlbmisc", "reserved1",
|
|
"badaddr", "config", "mpubase", "mpuacc",
|
|
"res16", "res17", "res18", "res19",
|
|
"res20", "res21", "res22", "res23",
|
|
"res24", "res25", "res26", "res27",
|
|
"res28", "res29", "res30", "res31",
|
|
};
|
|
#endif
|
|
|
|
#include "exec/gen-icount.h"
|
|
|
|
/* generate intermediate code for basic block 'tb'. */
|
|
static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
|
{
|
|
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
|
CPUNios2State *env = cs->env_ptr;
|
|
Nios2CPU *cpu = env_archcpu(env);
|
|
int page_insns;
|
|
|
|
dc->mem_idx = cpu_mmu_index(env, false);
|
|
dc->cr_state = cpu->cr_state;
|
|
|
|
/* Bound the number of insns to execute to those left on the page. */
|
|
page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
|
|
dc->base.max_insns = MIN(page_insns, dc->base.max_insns);
|
|
}
|
|
|
|
static void nios2_tr_tb_start(DisasContextBase *db, CPUState *cs)
|
|
{
|
|
}
|
|
|
|
static void nios2_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
|
|
{
|
|
tcg_gen_insn_start(dcbase->pc_next);
|
|
}
|
|
|
|
static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
|
|
{
|
|
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
|
CPUNios2State *env = cs->env_ptr;
|
|
const Nios2Instruction *instr;
|
|
uint32_t code, pc;
|
|
uint8_t op;
|
|
|
|
pc = dc->base.pc_next;
|
|
dc->pc = pc;
|
|
dc->base.pc_next = pc + 4;
|
|
|
|
/* Decode an instruction */
|
|
code = cpu_ldl_code(env, pc);
|
|
op = get_opcode(code);
|
|
|
|
if (unlikely(op >= ARRAY_SIZE(i_type_instructions))) {
|
|
t_gen_helper_raise_exception(dc, EXCP_ILLEGAL);
|
|
return;
|
|
}
|
|
|
|
instr = &i_type_instructions[op];
|
|
instr->handler(dc, code, instr->flags);
|
|
}
|
|
|
|
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
|
|
{
|
|
DisasContext *dc = container_of(dcbase, DisasContext, base);
|
|
|
|
/* Indicate where the next block should start */
|
|
switch (dc->base.is_jmp) {
|
|
case DISAS_TOO_MANY:
|
|
case DISAS_UPDATE:
|
|
/* Save the current PC back into the CPU register */
|
|
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
|
|
tcg_gen_exit_tb(NULL, 0);
|
|
break;
|
|
|
|
case DISAS_JUMP:
|
|
/* The jump will already have updated the PC register */
|
|
tcg_gen_exit_tb(NULL, 0);
|
|
break;
|
|
|
|
case DISAS_NORETURN:
|
|
/* nothing more to generate */
|
|
break;
|
|
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static void nios2_tr_disas_log(const DisasContextBase *dcbase,
|
|
CPUState *cpu, FILE *logfile)
|
|
{
|
|
fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
|
|
target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
|
|
}
|
|
|
|
static const TranslatorOps nios2_tr_ops = {
|
|
.init_disas_context = nios2_tr_init_disas_context,
|
|
.tb_start = nios2_tr_tb_start,
|
|
.insn_start = nios2_tr_insn_start,
|
|
.translate_insn = nios2_tr_translate_insn,
|
|
.tb_stop = nios2_tr_tb_stop,
|
|
.disas_log = nios2_tr_disas_log,
|
|
};
|
|
|
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
|
{
|
|
DisasContext dc;
|
|
translator_loop(&nios2_tr_ops, &dc.base, cs, tb, max_insns);
|
|
}
|
|
|
|
void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|
{
|
|
Nios2CPU *cpu = NIOS2_CPU(cs);
|
|
CPUNios2State *env = &cpu->env;
|
|
int i;
|
|
|
|
qemu_fprintf(f, "IN: PC=%x %s\n", env->pc, lookup_symbol(env->pc));
|
|
|
|
for (i = 0; i < NUM_GP_REGS; i++) {
|
|
qemu_fprintf(f, "%9s=%8.8x ", gr_regnames[i], env->regs[i]);
|
|
if ((i + 1) % 4 == 0) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
int j;
|
|
|
|
for (i = j = 0; i < NUM_CR_REGS; i++) {
|
|
if (!nios2_cr_reserved(&cpu->cr_state[i])) {
|
|
qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
|
|
if (++j % 4 == 0) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
}
|
|
if (j % 4 != 0) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
if (cpu->mmu_present) {
|
|
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
|
|
env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
|
|
FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
|
|
env->mmu.tlbacc_wr);
|
|
}
|
|
#endif
|
|
qemu_fprintf(f, "\n\n");
|
|
}
|
|
|
|
void nios2_tcg_init(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_GP_REGS; i++) {
|
|
cpu_R[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUNios2State, regs[i]),
|
|
gr_regnames[i]);
|
|
}
|
|
cpu_pc = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUNios2State, pc), "pc");
|
|
}
|
|
|
|
void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb,
|
|
target_ulong *data)
|
|
{
|
|
env->pc = data[0];
|
|
}
|