73053f6228
Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-32-f4bug@amsat.org>
259 lines
14 KiB
Plaintext
259 lines
14 KiB
Plaintext
# MIPS SIMD Architecture Module instruction set
|
|
#
|
|
# Copyright (C) 2020 Philippe Mathieu-Daudé
|
|
#
|
|
# SPDX-License-Identifier: LGPL-2.1-or-later
|
|
#
|
|
# Reference:
|
|
# MIPS Architecture for Programmers Volume IV-j
|
|
# - The MIPS32 SIMD Architecture Module, Revision 1.12
|
|
# (Document Number: MD00866-2B-MSA32-AFP-01.12)
|
|
# - The MIPS64 SIMD Architecture Module, Revision 1.12
|
|
# (Document Number: MD00868-1D-MSA64-AFP-01.12)
|
|
|
|
&r rs rt rd sa
|
|
|
|
&msa_r df wd ws wt
|
|
&msa_bz df wt sa
|
|
&msa_ldi df wd sa
|
|
&msa_i df wd ws sa
|
|
&msa_bit df wd ws m
|
|
&msa_elm_df df wd ws n
|
|
&msa_elm wd ws
|
|
|
|
%elm_df 16:6 !function=elm_df
|
|
%elm_n 16:6 !function=elm_n
|
|
%bit_df 16:7 !function=bit_df
|
|
%bit_m 16:7 !function=bit_m
|
|
%2r_df_w 16:1 !function=plus_2
|
|
%3r_df_h 21:1 !function=plus_1
|
|
%3r_df_w 21:1 !function=plus_2
|
|
|
|
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
|
|
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
|
|
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
|
|
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
|
|
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
|
|
@elm ...... .......... ws:5 wd:5 ...... &msa_elm
|
|
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
|
|
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
|
|
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w
|
|
@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
|
|
@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
|
|
@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
|
|
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
|
|
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
|
|
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i
|
|
@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i df=0
|
|
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi
|
|
@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m
|
|
|
|
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
|
|
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
|
|
|
|
BZ_V 010001 01011 ..... ................ @bz_v
|
|
BNZ_V 010001 01111 ..... ................ @bz_v
|
|
BZ 010001 110 .. ..... ................ @bz
|
|
BNZ 010001 111 .. ..... ................ @bz
|
|
|
|
ANDI 011110 00 ........ ..... ..... 000000 @i8
|
|
ORI 011110 01 ........ ..... ..... 000000 @i8
|
|
NORI 011110 10 ........ ..... ..... 000000 @i8
|
|
XORI 011110 11 ........ ..... ..... 000000 @i8
|
|
BMNZI 011110 00 ........ ..... ..... 000001 @i8
|
|
BMZI 011110 01 ........ ..... ..... 000001 @i8
|
|
BSELI 011110 10 ........ ..... ..... 000001 @i8
|
|
SHF 011110 .. ........ ..... ..... 000010 @i8_df
|
|
|
|
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
|
|
SUBVI 011110 001 .. ..... ..... ..... 000110 @u5
|
|
MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5
|
|
MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5
|
|
MINI_S 011110 100 .. ..... ..... ..... 000110 @s5
|
|
MINI_U 011110 101 .. ..... ..... ..... 000110 @u5
|
|
|
|
CEQI 011110 000 .. ..... ..... ..... 000111 @s5
|
|
CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5
|
|
CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5
|
|
CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5
|
|
CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5
|
|
|
|
LDI 011110 110 .. .......... ..... 000111 @ldi
|
|
|
|
SLLI 011110 000 ....... ..... ..... 001001 @bit
|
|
SRAI 011110 001 ....... ..... ..... 001001 @bit
|
|
SRLI 011110 010 ....... ..... ..... 001001 @bit
|
|
BCLRI 011110 011 ....... ..... ..... 001001 @bit
|
|
BSETI 011110 100 ....... ..... ..... 001001 @bit
|
|
BNEGI 011110 101 ....... ..... ..... 001001 @bit
|
|
BINSLI 011110 110 ....... ..... ..... 001001 @bit
|
|
BINSRI 011110 111 ....... ..... ..... 001001 @bit
|
|
|
|
SAT_S 011110 000 ....... ..... ..... 001010 @bit
|
|
SAT_U 011110 001 ....... ..... ..... 001010 @bit
|
|
SRARI 011110 010 ....... ..... ..... 001010 @bit
|
|
SRLRI 011110 011 ....... ..... ..... 001010 @bit
|
|
|
|
SLL 011110 000.. ..... ..... ..... 001101 @3r
|
|
SRA 011110 001.. ..... ..... ..... 001101 @3r
|
|
SRL 011110 010.. ..... ..... ..... 001101 @3r
|
|
BCLR 011110 011.. ..... ..... ..... 001101 @3r
|
|
BSET 011110 100.. ..... ..... ..... 001101 @3r
|
|
BNEG 011110 101.. ..... ..... ..... 001101 @3r
|
|
BINSL 011110 110.. ..... ..... ..... 001101 @3r
|
|
BINSR 011110 111.. ..... ..... ..... 001101 @3r
|
|
|
|
ADDV 011110 000.. ..... ..... ..... 001110 @3r
|
|
SUBV 011110 001.. ..... ..... ..... 001110 @3r
|
|
MAX_S 011110 010.. ..... ..... ..... 001110 @3r
|
|
MAX_U 011110 011.. ..... ..... ..... 001110 @3r
|
|
MIN_S 011110 100.. ..... ..... ..... 001110 @3r
|
|
MIN_U 011110 101.. ..... ..... ..... 001110 @3r
|
|
MAX_A 011110 110.. ..... ..... ..... 001110 @3r
|
|
MIN_A 011110 111.. ..... ..... ..... 001110 @3r
|
|
|
|
CEQ 011110 000.. ..... ..... ..... 001111 @3r
|
|
CLT_S 011110 010.. ..... ..... ..... 001111 @3r
|
|
CLT_U 011110 011.. ..... ..... ..... 001111 @3r
|
|
CLE_S 011110 100.. ..... ..... ..... 001111 @3r
|
|
CLE_U 011110 101.. ..... ..... ..... 001111 @3r
|
|
|
|
ADD_A 011110 000.. ..... ..... ..... 010000 @3r
|
|
ADDS_A 011110 001.. ..... ..... ..... 010000 @3r
|
|
ADDS_S 011110 010.. ..... ..... ..... 010000 @3r
|
|
ADDS_U 011110 011.. ..... ..... ..... 010000 @3r
|
|
AVE_S 011110 100.. ..... ..... ..... 010000 @3r
|
|
AVE_U 011110 101.. ..... ..... ..... 010000 @3r
|
|
AVER_S 011110 110.. ..... ..... ..... 010000 @3r
|
|
AVER_U 011110 111.. ..... ..... ..... 010000 @3r
|
|
|
|
SUBS_S 011110 000.. ..... ..... ..... 010001 @3r
|
|
SUBS_U 011110 001.. ..... ..... ..... 010001 @3r
|
|
SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r
|
|
SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r
|
|
ASUB_S 011110 100.. ..... ..... ..... 010001 @3r
|
|
ASUB_U 011110 101.. ..... ..... ..... 010001 @3r
|
|
|
|
MULV 011110 000.. ..... ..... ..... 010010 @3r
|
|
MADDV 011110 001.. ..... ..... ..... 010010 @3r
|
|
MSUBV 011110 010.. ..... ..... ..... 010010 @3r
|
|
DIV_S 011110 100.. ..... ..... ..... 010010 @3r
|
|
DIV_U 011110 101.. ..... ..... ..... 010010 @3r
|
|
MOD_S 011110 110.. ..... ..... ..... 010010 @3r
|
|
MOD_U 011110 111.. ..... ..... ..... 010010 @3r
|
|
|
|
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
|
|
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
|
|
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
|
|
DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
|
|
DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
|
|
DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
|
|
|
|
SLD 011110 000 .. ..... ..... ..... 010100 @3r
|
|
SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
|
|
PCKEV 011110 010 .. ..... ..... ..... 010100 @3r
|
|
PCKOD 011110 011 .. ..... ..... ..... 010100 @3r
|
|
ILVL 011110 100 .. ..... ..... ..... 010100 @3r
|
|
ILVR 011110 101 .. ..... ..... ..... 010100 @3r
|
|
ILVEV 011110 110 .. ..... ..... ..... 010100 @3r
|
|
ILVOD 011110 111 .. ..... ..... ..... 010100 @3r
|
|
|
|
VSHF 011110 000 .. ..... ..... ..... 010101 @3r
|
|
SRAR 011110 001 .. ..... ..... ..... 010101 @3r
|
|
SRLR 011110 010 .. ..... ..... ..... 010101 @3r
|
|
HADD_S 011110 100.. ..... ..... ..... 010101 @3r
|
|
HADD_U 011110 101.. ..... ..... ..... 010101 @3r
|
|
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
|
|
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
|
|
|
|
{
|
|
CTCMSA 011110 0000111110 ..... ..... 011001 @elm
|
|
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
|
|
}
|
|
{
|
|
CFCMSA 011110 0001111110 ..... ..... 011001 @elm
|
|
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
|
|
}
|
|
{
|
|
MOVE_V 011110 0010111110 ..... ..... 011001 @elm
|
|
COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
|
|
}
|
|
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
|
|
INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
|
|
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
|
|
|
|
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w
|
|
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w
|
|
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w
|
|
FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w
|
|
FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w
|
|
FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w
|
|
FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w
|
|
FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w
|
|
FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w
|
|
FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w
|
|
FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w
|
|
FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w
|
|
FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w
|
|
FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w
|
|
FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w
|
|
FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w
|
|
|
|
FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w
|
|
FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w
|
|
FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w
|
|
FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w
|
|
FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w
|
|
FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w
|
|
FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w
|
|
FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w
|
|
FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w
|
|
FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w
|
|
FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w
|
|
FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w
|
|
FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w
|
|
|
|
FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w
|
|
FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w
|
|
FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w
|
|
MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h
|
|
MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h
|
|
MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h
|
|
FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w
|
|
FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w
|
|
FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w
|
|
MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h
|
|
MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h
|
|
MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h
|
|
|
|
AND_V 011110 00000 ..... ..... ..... 011110 @vec
|
|
OR_V 011110 00001 ..... ..... ..... 011110 @vec
|
|
NOR_V 011110 00010 ..... ..... ..... 011110 @vec
|
|
XOR_V 011110 00011 ..... ..... ..... 011110 @vec
|
|
BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec
|
|
BMZ_V 011110 00101 ..... ..... ..... 011110 @vec
|
|
BSEL_V 011110 00110 ..... ..... ..... 011110 @vec
|
|
FILL 011110 11000000 .. ..... ..... 011110 @2r
|
|
PCNT 011110 11000001 .. ..... ..... 011110 @2r
|
|
NLOC 011110 11000010 .. ..... ..... 011110 @2r
|
|
NLZC 011110 11000011 .. ..... ..... 011110 @2r
|
|
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
|
|
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
|
|
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
|
|
FSQRT 011110 110010011 . ..... ..... 011110 @2rf
|
|
FRSQRT 011110 110010100 . ..... ..... 011110 @2rf
|
|
FRCP 011110 110010101 . ..... ..... 011110 @2rf
|
|
FRINT 011110 110010110 . ..... ..... 011110 @2rf
|
|
FLOG2 011110 110010111 . ..... ..... 011110 @2rf
|
|
FEXUPL 011110 110011000 . ..... ..... 011110 @2rf
|
|
FEXUPR 011110 110011001 . ..... ..... 011110 @2rf
|
|
FFQL 011110 110011010 . ..... ..... 011110 @2rf
|
|
FFQR 011110 110011011 . ..... ..... 011110 @2rf
|
|
FTINT_S 011110 110011100 . ..... ..... 011110 @2rf
|
|
FTINT_U 011110 110011101 . ..... ..... 011110 @2rf
|
|
FFINT_S 011110 110011110 . ..... ..... 011110 @2rf
|
|
FFINT_U 011110 110011111 . ..... ..... 011110 @2rf
|
|
|
|
LD 011110 .......... ..... ..... 1000 .. @ldst
|
|
ST 011110 .......... ..... ..... 1001 .. @ldst
|