744 lines
21 KiB
C
744 lines
21 KiB
C
#include "sysemu/sysemu.h"
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#include "cpu.h"
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#include "sysemu/sysemu.h"
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#include "helper_regs.h"
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#include "hw/spapr.h"
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#define HPTES_PER_GROUP 8
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#define HPTE_V_SSIZE_SHIFT 62
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#define HPTE_V_AVPN_SHIFT 7
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#define HPTE_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
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#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
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#define HPTE_V_BOLTED 0x0000000000000010ULL
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#define HPTE_V_LOCK 0x0000000000000008ULL
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#define HPTE_V_LARGE 0x0000000000000004ULL
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#define HPTE_V_SECONDARY 0x0000000000000002ULL
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#define HPTE_V_VALID 0x0000000000000001ULL
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#define HPTE_R_PP0 0x8000000000000000ULL
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#define HPTE_R_TS 0x4000000000000000ULL
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#define HPTE_R_KEY_HI 0x3000000000000000ULL
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#define HPTE_R_RPN_SHIFT 12
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#define HPTE_R_RPN 0x3ffffffffffff000ULL
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#define HPTE_R_FLAGS 0x00000000000003ffULL
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#define HPTE_R_PP 0x0000000000000003ULL
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#define HPTE_R_N 0x0000000000000004ULL
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#define HPTE_R_G 0x0000000000000008ULL
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#define HPTE_R_M 0x0000000000000010ULL
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#define HPTE_R_I 0x0000000000000020ULL
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#define HPTE_R_W 0x0000000000000040ULL
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#define HPTE_R_WIMG 0x0000000000000078ULL
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#define HPTE_R_C 0x0000000000000080ULL
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#define HPTE_R_R 0x0000000000000100ULL
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#define HPTE_R_KEY_LO 0x0000000000000e00ULL
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#define HPTE_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
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target_ulong pte_index)
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{
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target_ulong rb, va_low;
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rb = (v & ~0x7fULL) << 16; /* AVA field */
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY) {
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va_low = ~va_low;
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}
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/* xor vsid from AVA */
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if (!(v & HPTE_V_1TB_SEG)) {
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va_low ^= v >> 12;
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} else {
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va_low ^= v >> 24;
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}
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va_low &= 0x7ff;
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if (v & HPTE_V_LARGE) {
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rb |= 1; /* L field */
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#if 0 /* Disable that P7 specific bit for now */
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if (r & 0xff000) {
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/* non-16MB large page, must be 64k */
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field */
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}
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#endif
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} else {
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/* 4kB page */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */
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}
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rb |= (v >> 54) & 0x300; /* B field */
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return rb;
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}
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static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong pteh = args[2];
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target_ulong ptel = args[3];
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target_ulong page_shift = 12;
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target_ulong raddr;
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target_ulong i;
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uint8_t *hpte;
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/* only handle 4k and 16M pages for now */
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if (pteh & HPTE_V_LARGE) {
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#if 0 /* We don't support 64k pages yet */
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if ((ptel & 0xf000) == 0x1000) {
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/* 64k page */
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} else
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#endif
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if ((ptel & 0xff000) == 0) {
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/* 16M page */
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page_shift = 24;
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/* lowest AVA bit must be 0 for 16M pages */
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if (pteh & 0x80) {
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return H_PARAMETER;
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}
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} else {
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return H_PARAMETER;
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}
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}
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raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1);
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if (raddr < spapr->ram_limit) {
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/* Regular RAM - should have WIMG=0010 */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
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return H_PARAMETER;
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}
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} else {
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/* Looks like an IO address */
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/* FIXME: What WIMG combinations could be sensible for IO?
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* For now we allow WIMG=010x, but are there others? */
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/* FIXME: Should we check against registered IO addresses? */
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if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
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return H_PARAMETER;
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}
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}
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pteh &= ~0x60ULL;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7ULL;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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for (i = 0; ; ++i) {
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if (i == 8) {
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return H_PTEG_FULL;
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}
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if ((ldq_p(hpte) & HPTE_V_VALID) == 0) {
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break;
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}
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hpte += HASH_PTE_SIZE_64;
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}
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} else {
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i = 0;
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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if (ldq_p(hpte) & HPTE_V_VALID) {
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return H_PTEG_FULL;
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}
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}
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stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
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/* eieio(); FIXME: need some sort of barrier for smp? */
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stq_p(hpte, pteh);
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args[0] = pte_index + i;
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return H_SUCCESS;
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}
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enum {
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REMOVE_SUCCESS = 0,
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REMOVE_NOT_FOUND = 1,
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REMOVE_PARM = 2,
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REMOVE_HW = 3,
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};
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static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex,
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target_ulong avpn,
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target_ulong flags,
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target_ulong *vp, target_ulong *rp)
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{
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uint8_t *hpte;
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target_ulong v, r, rb;
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if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return REMOVE_PARM;
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}
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hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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if ((v & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
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return REMOVE_NOT_FOUND;
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}
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*vp = v;
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*rp = r;
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stq_p(hpte, 0);
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rb = compute_tlbie_rb(v, r, ptex);
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ppc_tlb_invalidate_one(env, rb);
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return REMOVE_SUCCESS;
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}
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static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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int ret;
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ret = remove_hpte(env, pte_index, avpn, flags,
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&args[0], &args[1]);
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switch (ret) {
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case REMOVE_SUCCESS:
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return H_SUCCESS;
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case REMOVE_NOT_FOUND:
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return H_NOT_FOUND;
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case REMOVE_PARM:
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return H_PARAMETER;
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case REMOVE_HW:
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return H_HARDWARE;
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}
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assert(0);
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}
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#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
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#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
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#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
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#define H_BULK_REMOVE_END 0xc000000000000000ULL
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#define H_BULK_REMOVE_CODE 0x3000000000000000ULL
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#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
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#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
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#define H_BULK_REMOVE_PARM 0x2000000000000000ULL
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#define H_BULK_REMOVE_HW 0x3000000000000000ULL
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#define H_BULK_REMOVE_RC 0x0c00000000000000ULL
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#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
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#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
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#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
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#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
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#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
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#define H_BULK_REMOVE_MAX_BATCH 4
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static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUPPCState *env = &cpu->env;
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int i;
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for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
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target_ulong *tsh = &args[i*2];
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target_ulong tsl = args[i*2 + 1];
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target_ulong v, r, ret;
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if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
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break;
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} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
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return H_PARAMETER;
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}
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*tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
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*tsh |= H_BULK_REMOVE_RESPONSE;
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if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
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*tsh |= H_BULK_REMOVE_PARM;
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return H_PARAMETER;
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}
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ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl,
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(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
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&v, &r);
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*tsh |= ret << 60;
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switch (ret) {
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case REMOVE_SUCCESS:
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*tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
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break;
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case REMOVE_PARM:
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return H_PARAMETER;
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case REMOVE_HW:
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return H_HARDWARE;
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}
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}
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return H_SUCCESS;
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}
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static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong avpn = args[2];
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uint8_t *hpte;
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target_ulong v, r, rb;
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
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return H_PARAMETER;
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}
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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v = ldq_p(hpte);
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r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
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if ((v & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
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return H_NOT_FOUND;
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}
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r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
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HPTE_R_KEY_HI | HPTE_R_KEY_LO);
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r |= (flags << 55) & HPTE_R_PP0;
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r |= (flags << 48) & HPTE_R_KEY_HI;
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r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
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rb = compute_tlbie_rb(v, r, pte_index);
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stq_p(hpte, v & ~HPTE_V_VALID);
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ppc_tlb_invalidate_one(env, rb);
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stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
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/* Don't need a memory barrier, due to qemu's global lock */
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stq_p(hpte, v);
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return H_SUCCESS;
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}
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static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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/* FIXME: actually implement this */
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return H_HARDWARE;
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}
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#define FLAGS_REGISTER_VPA 0x0000200000000000ULL
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#define FLAGS_REGISTER_DTL 0x0000400000000000ULL
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#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
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#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
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#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
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#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
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#define VPA_MIN_SIZE 640
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#define VPA_SIZE_OFFSET 0x4
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#define VPA_SHARED_PROC_OFFSET 0x9
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#define VPA_SHARED_PROC_VAL 0x2
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static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
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{
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uint16_t size;
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uint8_t tmp;
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if (vpa == 0) {
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hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
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return H_HARDWARE;
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}
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if (vpa % env->dcache_line_size) {
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return H_PARAMETER;
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}
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/* FIXME: bounds check the address */
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size = lduw_be_phys(vpa + 0x4);
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if (size < VPA_MIN_SIZE) {
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return H_PARAMETER;
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}
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/* VPA is not allowed to cross a page boundary */
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if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
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return H_PARAMETER;
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}
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env->vpa_addr = vpa;
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tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET);
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tmp |= VPA_SHARED_PROC_VAL;
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stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
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return H_SUCCESS;
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}
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static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
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{
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if (env->slb_shadow_addr) {
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return H_RESOURCE;
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}
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if (env->dtl_addr) {
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return H_RESOURCE;
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}
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env->vpa_addr = 0;
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return H_SUCCESS;
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}
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static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
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{
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uint32_t size;
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if (addr == 0) {
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hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
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return H_HARDWARE;
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}
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size = ldl_be_phys(addr + 0x4);
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if (size < 0x8) {
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return H_PARAMETER;
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}
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if ((addr / 4096) != ((addr + size - 1) / 4096)) {
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return H_PARAMETER;
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}
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if (!env->vpa_addr) {
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return H_RESOURCE;
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}
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env->slb_shadow_addr = addr;
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env->slb_shadow_size = size;
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return H_SUCCESS;
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}
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static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
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{
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env->slb_shadow_addr = 0;
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env->slb_shadow_size = 0;
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return H_SUCCESS;
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}
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static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
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{
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uint32_t size;
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if (addr == 0) {
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hcall_dprintf("Can't cope with DTL at logical 0\n");
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return H_HARDWARE;
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}
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size = ldl_be_phys(addr + 0x4);
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if (size < 48) {
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return H_PARAMETER;
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}
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if (!env->vpa_addr) {
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return H_RESOURCE;
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}
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env->dtl_addr = addr;
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env->dtl_size = size;
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return H_SUCCESS;
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}
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static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
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{
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env->dtl_addr = 0;
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env->dtl_size = 0;
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return H_SUCCESS;
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}
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static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong flags = args[0];
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target_ulong procno = args[1];
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target_ulong vpa = args[2];
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target_ulong ret = H_PARAMETER;
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CPUPPCState *tenv;
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for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
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if (tenv->cpu_index == procno) {
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break;
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}
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}
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if (!tenv) {
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return H_PARAMETER;
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}
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switch (flags) {
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case FLAGS_REGISTER_VPA:
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ret = register_vpa(tenv, vpa);
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break;
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case FLAGS_DEREGISTER_VPA:
|
|
ret = deregister_vpa(tenv, vpa);
|
|
break;
|
|
|
|
case FLAGS_REGISTER_SLBSHADOW:
|
|
ret = register_slb_shadow(tenv, vpa);
|
|
break;
|
|
|
|
case FLAGS_DEREGISTER_SLBSHADOW:
|
|
ret = deregister_slb_shadow(tenv, vpa);
|
|
break;
|
|
|
|
case FLAGS_REGISTER_DTL:
|
|
ret = register_dtl(tenv, vpa);
|
|
break;
|
|
|
|
case FLAGS_DEREGISTER_DTL:
|
|
ret = deregister_dtl(tenv, vpa);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
env->msr |= (1ULL << MSR_EE);
|
|
hreg_compute_hflags(env);
|
|
if (!cpu_has_work(CPU(cpu))) {
|
|
env->halted = 1;
|
|
env->exception_index = EXCP_HLT;
|
|
env->exit_request = 1;
|
|
}
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong rtas_r3 = args[0];
|
|
uint32_t token = ldl_be_phys(rtas_r3);
|
|
uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
|
|
uint32_t nret = ldl_be_phys(rtas_r3 + 8);
|
|
|
|
return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12,
|
|
nret, rtas_r3 + 12 + 4*nargs);
|
|
}
|
|
|
|
static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong size = args[0];
|
|
target_ulong addr = args[1];
|
|
|
|
switch (size) {
|
|
case 1:
|
|
args[0] = ldub_phys(addr);
|
|
return H_SUCCESS;
|
|
case 2:
|
|
args[0] = lduw_phys(addr);
|
|
return H_SUCCESS;
|
|
case 4:
|
|
args[0] = ldl_phys(addr);
|
|
return H_SUCCESS;
|
|
case 8:
|
|
args[0] = ldq_phys(addr);
|
|
return H_SUCCESS;
|
|
}
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong size = args[0];
|
|
target_ulong addr = args[1];
|
|
target_ulong val = args[2];
|
|
|
|
switch (size) {
|
|
case 1:
|
|
stb_phys(addr, val);
|
|
return H_SUCCESS;
|
|
case 2:
|
|
stw_phys(addr, val);
|
|
return H_SUCCESS;
|
|
case 4:
|
|
stl_phys(addr, val);
|
|
return H_SUCCESS;
|
|
case 8:
|
|
stq_phys(addr, val);
|
|
return H_SUCCESS;
|
|
}
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong dst = args[0]; /* Destination address */
|
|
target_ulong src = args[1]; /* Source address */
|
|
target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
|
|
target_ulong count = args[3]; /* Element count */
|
|
target_ulong op = args[4]; /* 0 = copy, 1 = invert */
|
|
uint64_t tmp;
|
|
unsigned int mask = (1 << esize) - 1;
|
|
int step = 1 << esize;
|
|
|
|
if (count > 0x80000000) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
if ((dst & mask) || (src & mask) || (op > 1)) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
if (dst >= src && dst < (src + (count << esize))) {
|
|
dst = dst + ((count - 1) << esize);
|
|
src = src + ((count - 1) << esize);
|
|
step = -step;
|
|
}
|
|
|
|
while (count--) {
|
|
switch (esize) {
|
|
case 0:
|
|
tmp = ldub_phys(src);
|
|
break;
|
|
case 1:
|
|
tmp = lduw_phys(src);
|
|
break;
|
|
case 2:
|
|
tmp = ldl_phys(src);
|
|
break;
|
|
case 3:
|
|
tmp = ldq_phys(src);
|
|
break;
|
|
default:
|
|
return H_PARAMETER;
|
|
}
|
|
if (op == 1) {
|
|
tmp = ~tmp;
|
|
}
|
|
switch (esize) {
|
|
case 0:
|
|
stb_phys(dst, tmp);
|
|
break;
|
|
case 1:
|
|
stw_phys(dst, tmp);
|
|
break;
|
|
case 2:
|
|
stl_phys(dst, tmp);
|
|
break;
|
|
case 3:
|
|
stq_phys(dst, tmp);
|
|
break;
|
|
}
|
|
dst = dst + step;
|
|
src = src + step;
|
|
}
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
|
|
static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
|
|
|
|
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
|
|
{
|
|
spapr_hcall_fn *slot;
|
|
|
|
if (opcode <= MAX_HCALL_OPCODE) {
|
|
assert((opcode & 0x3) == 0);
|
|
|
|
slot = &papr_hypercall_table[opcode / 4];
|
|
} else {
|
|
assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
|
|
|
|
slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
|
|
}
|
|
|
|
assert(!(*slot));
|
|
*slot = fn;
|
|
}
|
|
|
|
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
|
|
target_ulong *args)
|
|
{
|
|
if ((opcode <= MAX_HCALL_OPCODE)
|
|
&& ((opcode & 0x3) == 0)) {
|
|
spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
|
|
|
|
if (fn) {
|
|
return fn(cpu, spapr, opcode, args);
|
|
}
|
|
} else if ((opcode >= KVMPPC_HCALL_BASE) &&
|
|
(opcode <= KVMPPC_HCALL_MAX)) {
|
|
spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
|
|
|
|
if (fn) {
|
|
return fn(cpu, spapr, opcode, args);
|
|
}
|
|
}
|
|
|
|
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
|
|
return H_FUNCTION;
|
|
}
|
|
|
|
static void hypercall_register_types(void)
|
|
{
|
|
/* hcall-pft */
|
|
spapr_register_hypercall(H_ENTER, h_enter);
|
|
spapr_register_hypercall(H_REMOVE, h_remove);
|
|
spapr_register_hypercall(H_PROTECT, h_protect);
|
|
|
|
/* hcall-bulk */
|
|
spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
|
|
|
|
/* hcall-dabr */
|
|
spapr_register_hypercall(H_SET_DABR, h_set_dabr);
|
|
|
|
/* hcall-splpar */
|
|
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
|
|
spapr_register_hypercall(H_CEDE, h_cede);
|
|
|
|
/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
|
|
* here between the "CI" and the "CACHE" variants, they will use whatever
|
|
* mapping attributes qemu is using. When using KVM, the kernel will
|
|
* enforce the attributes more strongly
|
|
*/
|
|
spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
|
|
spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
|
|
spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
|
|
spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
|
|
spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
|
|
spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
|
|
spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
|
|
|
|
/* qemu/KVM-PPC specific hcalls */
|
|
spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
|
|
}
|
|
|
|
type_init(hypercall_register_types)
|