18e08a5529
pci.h declares some functions which aren't defined in pci.h. Clean up moving things to appropriate headers, and update all users. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
279 lines
7.1 KiB
C
279 lines
7.1 KiB
C
/*
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* Renesas SH7751R R2D-PLUS emulation
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*
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* Copyright (c) 2007 Magnus Damm
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* Copyright (c) 2008 Paul Mundt
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sh.h"
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#include "devices.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "pci.h"
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#include "sh_pci.h"
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#include "net.h"
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#include "sh7750_regs.h"
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#include "ide.h"
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#include "loader.h"
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#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
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#define SDRAM_SIZE 0x04000000
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#define SM501_VRAM_SIZE 0x800000
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/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
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#define LINUX_LOAD_OFFSET 0x800000
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#define PA_IRLMSK 0x00
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#define PA_POWOFF 0x30
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#define PA_VERREG 0x32
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#define PA_OUTPORT 0x36
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typedef struct {
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uint16_t bcr;
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uint16_t irlmsk;
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uint16_t irlmon;
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uint16_t cfctl;
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uint16_t cfpow;
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uint16_t dispctl;
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uint16_t sdmpow;
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uint16_t rtcce;
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uint16_t pcicd;
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uint16_t voyagerrts;
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uint16_t cfrst;
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uint16_t admrts;
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uint16_t extrst;
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uint16_t cfcdintclr;
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uint16_t keyctlclr;
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uint16_t pad0;
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uint16_t pad1;
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uint16_t powoff;
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uint16_t verreg;
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uint16_t inport;
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uint16_t outport;
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uint16_t bverreg;
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/* output pin */
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qemu_irq irl;
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} r2d_fpga_t;
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enum r2d_fpga_irq {
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PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
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SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
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NR_IRQS
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};
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static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
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[CF_IDE] = { 1, 1<<9 },
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[CF_CD] = { 2, 1<<8 },
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[PCI_INTA] = { 9, 1<<14 },
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[PCI_INTB] = { 10, 1<<13 },
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[PCI_INTC] = { 3, 1<<12 },
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[PCI_INTD] = { 0, 1<<11 },
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[SM501] = { 4, 1<<10 },
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[KEY] = { 5, 1<<6 },
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[RTC_A] = { 6, 1<<5 },
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[RTC_T] = { 7, 1<<4 },
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[SDCARD] = { 8, 1<<7 },
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[EXT] = { 11, 1<<0 },
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[TP] = { 12, 1<<15 },
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};
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static void update_irl(r2d_fpga_t *fpga)
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{
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int i, irl = 15;
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for (i = 0; i < NR_IRQS; i++)
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if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
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if (irqtab[i].irl < irl)
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irl = irqtab[i].irl;
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qemu_set_irq(fpga->irl, irl ^ 15);
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}
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static void r2d_fpga_irq_set(void *opaque, int n, int level)
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{
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r2d_fpga_t *fpga = opaque;
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if (level)
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fpga->irlmon |= irqtab[n].msk;
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else
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fpga->irlmon &= ~irqtab[n].msk;
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update_irl(fpga);
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}
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static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
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{
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r2d_fpga_t *s = opaque;
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switch (addr) {
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case PA_IRLMSK:
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return s->irlmsk;
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case PA_OUTPORT:
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return s->outport;
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case PA_POWOFF:
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return s->powoff;
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case PA_VERREG:
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return 0x10;
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}
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return 0;
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}
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static void
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r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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r2d_fpga_t *s = opaque;
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switch (addr) {
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case PA_IRLMSK:
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s->irlmsk = value;
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update_irl(s);
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break;
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case PA_OUTPORT:
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s->outport = value;
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break;
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case PA_POWOFF:
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s->powoff = value;
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break;
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case PA_VERREG:
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/* Discard writes */
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break;
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}
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}
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static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
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r2d_fpga_read,
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r2d_fpga_read,
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NULL,
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};
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static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
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r2d_fpga_write,
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r2d_fpga_write,
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NULL,
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};
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static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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{
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int iomemtype;
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r2d_fpga_t *s;
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s = qemu_mallocz(sizeof(r2d_fpga_t));
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s->irl = irl;
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iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
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r2d_fpga_writefn, s);
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cpu_register_physical_memory(base, 0x40, iomemtype);
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return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
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}
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static void r2d_pci_set_irq(void *opaque, int n, int l)
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{
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qemu_irq *p = opaque;
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qemu_set_irq(p[n], l);
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}
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static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
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{
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const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
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return intx[d->devfn >> 3];
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}
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static void r2d_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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struct SH7750State *s;
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ram_addr_t sdram_addr;
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qemu_irq *irq;
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PCIBus *pci;
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DriveInfo *dinfo;
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int i;
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if (!cpu_model)
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cpu_model = "SH7751R";
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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/* Allocate memory space */
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sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
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cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
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/* Register peripherals */
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s = sh7750_init(env);
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irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
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pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
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sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
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/* onboard CF (True IDE mode, Master only). */
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if ((dinfo = drive_get(IF_IDE, 0, 0)) != NULL)
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mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
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dinfo, NULL);
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/* NIC: rtl8139 on-board, and 2 slots. */
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for (i = 0; i < nb_nics; i++)
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pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
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/* Todo: register on board registers */
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if (kernel_filename) {
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int kernel_size;
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/* initialization which should be done by firmware */
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stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
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stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
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if (kernel_cmdline) {
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kernel_size = load_image_targphys(kernel_filename,
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SDRAM_BASE + LINUX_LOAD_OFFSET,
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SDRAM_SIZE - LINUX_LOAD_OFFSET);
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env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
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pstrcpy_targphys("cmdline", SDRAM_BASE + 0x10100, 256, kernel_cmdline);
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} else {
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kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE, SDRAM_SIZE);
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env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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exit(1);
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}
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}
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}
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static QEMUMachine r2d_machine = {
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.name = "r2d",
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.desc = "r2d-plus board",
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.init = r2d_init,
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};
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static void r2d_machine_init(void)
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{
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qemu_register_machine(&r2d_machine);
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}
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machine_init(r2d_machine_init);
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