467 lines
13 KiB
C
467 lines
13 KiB
C
/*
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* QEMU Sparc SLAVIO interrupt controller emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sun4m.h"
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#include "monitor.h"
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#include "sysbus.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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/*
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* Registers of interrupt controller in sun4m.
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*
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* This is the interrupt controller part of chip STP2001 (Slave I/O), also
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* produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* There is a system master controller and one for each cpu.
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*
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*/
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#define MAX_CPUS 16
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#define MAX_PILS 16
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struct SLAVIO_INTCTLState;
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typedef struct SLAVIO_CPUINTCTLState {
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uint32_t intreg_pending;
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struct SLAVIO_INTCTLState *master;
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uint32_t cpu;
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uint32_t irl_out;
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} SLAVIO_CPUINTCTLState;
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typedef struct SLAVIO_INTCTLState {
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SysBusDevice busdev;
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uint32_t intregm_pending;
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uint32_t intregm_disabled;
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uint32_t target_cpu;
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count[32];
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#endif
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qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
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SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
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} SLAVIO_INTCTLState;
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#define INTCTL_MAXADDR 0xf
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#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
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#define INTCTLM_SIZE 0x14
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#define MASTER_IRQ_MASK ~0x0fa2007f
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#define MASTER_DISABLE 0x80000000
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#define CPU_SOFTIRQ_MASK 0xfffe0000
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#define CPU_IRQ_INT15_IN (1 << 15)
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#define CPU_IRQ_TIMER_IN (1 << 14)
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
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// per-cpu interrupt controller
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static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_CPUINTCTLState *s = opaque;
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uint32_t saddr, ret;
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saddr = addr >> 2;
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switch (saddr) {
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case 0:
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ret = s->intreg_pending;
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break;
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default:
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ret = 0;
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break;
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}
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DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
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return ret;
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}
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SLAVIO_CPUINTCTLState *s = opaque;
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uint32_t saddr;
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saddr = addr >> 2;
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DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
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switch (saddr) {
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case 1: // clear pending softints
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val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
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s->intreg_pending &= ~val;
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slavio_check_interrupts(s->master, 1);
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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s->intreg_pending);
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break;
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case 2: // set softint
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val &= CPU_SOFTIRQ_MASK;
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s->intreg_pending |= val;
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slavio_check_interrupts(s->master, 1);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
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s->intreg_pending);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
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NULL,
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NULL,
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slavio_intctl_mem_readl,
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};
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static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
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NULL,
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NULL,
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slavio_intctl_mem_writel,
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};
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// master system interrupt controller
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static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr, ret;
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saddr = addr >> 2;
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switch (saddr) {
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case 0:
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ret = s->intregm_pending & ~MASTER_DISABLE;
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break;
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case 1:
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ret = s->intregm_disabled & MASTER_IRQ_MASK;
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break;
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case 4:
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ret = s->target_cpu;
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break;
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default:
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ret = 0;
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break;
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}
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DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
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return ret;
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}
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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saddr = addr >> 2;
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DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
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switch (saddr) {
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case 2: // clear (enable)
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// Force clear unused bits
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val &= MASTER_IRQ_MASK;
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s->intregm_disabled &= ~val;
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled);
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slavio_check_interrupts(s, 1);
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break;
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case 3: // set (disable, clear pending)
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// Force clear unused bits
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val &= MASTER_IRQ_MASK;
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s->intregm_disabled |= val;
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s->intregm_pending &= ~val;
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slavio_check_interrupts(s, 1);
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DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
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s->intregm_disabled);
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break;
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case 4:
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s->target_cpu = val & (MAX_CPUS - 1);
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slavio_check_interrupts(s, 1);
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DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
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NULL,
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NULL,
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slavio_intctlm_mem_readl,
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};
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static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
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NULL,
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NULL,
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slavio_intctlm_mem_writel,
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};
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void slavio_pic_info(Monitor *mon, DeviceState *dev)
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{
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SysBusDevice *sd;
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SLAVIO_INTCTLState *s;
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int i;
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sd = sysbus_from_qdev(dev);
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s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
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for (i = 0; i < MAX_CPUS; i++) {
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monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
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s->slaves[i].intreg_pending);
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}
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monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
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s->intregm_pending, s->intregm_disabled);
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}
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void slavio_irq_info(Monitor *mon, DeviceState *dev)
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{
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#ifndef DEBUG_IRQ_COUNT
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monitor_printf(mon, "irq statistic code not compiled.\n");
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#else
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SysBusDevice *sd;
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SLAVIO_INTCTLState *s;
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int i;
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int64_t count;
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sd = sysbus_from_qdev(dev);
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s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
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monitor_printf(mon, "IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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count = s->irq_count[i];
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if (count > 0)
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monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
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}
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#endif
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}
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static const uint32_t intbit_to_level[] = {
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2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
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};
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static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
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{
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uint32_t pending = s->intregm_pending, pil_pending;
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unsigned int i, j;
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pending &= ~s->intregm_disabled;
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DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
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for (i = 0; i < MAX_CPUS; i++) {
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pil_pending = 0;
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/* If we are the current interrupt target, get hard interrupts */
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if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
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(i == s->target_cpu)) {
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for (j = 0; j < 32; j++) {
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if ((pending & (1 << j)) && intbit_to_level[j]) {
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pil_pending |= 1 << intbit_to_level[j];
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}
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}
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}
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/* Calculate current pending hard interrupts for display */
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s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
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CPU_IRQ_TIMER_IN;
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if (i == s->target_cpu) {
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for (j = 0; j < 32; j++) {
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if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
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s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
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}
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}
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}
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/* Level 15 and CPU timer interrupts are not maskable */
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pil_pending |= s->slaves[i].intreg_pending &
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(CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
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/* Add soft interrupts */
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pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
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if (set_irqs) {
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for (j = MAX_PILS; j > 0; j--) {
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if (pil_pending & (1 << j)) {
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if (!(s->slaves[i].irl_out & (1 << j))) {
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qemu_irq_raise(s->cpu_irqs[i][j]);
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}
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} else {
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if (s->slaves[i].irl_out & (1 << j)) {
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qemu_irq_lower(s->cpu_irqs[i][j]);
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}
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}
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}
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}
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s->slaves[i].irl_out = pil_pending;
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}
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}
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/*
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* "irq" here is the bit number in the system interrupt register to
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* separate serial and keyboard interrupts sharing a level.
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*/
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static void slavio_set_irq(void *opaque, int irq, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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unsigned int i;
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DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
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level);
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if (pil > 0) {
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if (level) {
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[pil]++;
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#endif
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s->intregm_pending |= mask;
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if (pil == 15) {
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for (i = 0; i < MAX_CPUS; i++) {
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s->slaves[i].intreg_pending |= 1 << pil;
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}
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}
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} else {
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s->intregm_pending &= ~mask;
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if (pil == 15) {
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for (i = 0; i < MAX_CPUS; i++) {
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s->slaves[i].intreg_pending &= ~(1 << pil);
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}
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}
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}
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slavio_check_interrupts(s, 1);
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}
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}
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static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
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if (level) {
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s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
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} else {
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s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
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}
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slavio_check_interrupts(s, 1);
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}
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static void slavio_set_irq_all(void *opaque, int irq, int level)
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{
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if (irq < 32) {
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slavio_set_irq(opaque, irq, level);
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} else {
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slavio_set_timer_irq_cpu(opaque, irq - 32, level);
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}
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}
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static int vmstate_intctl_post_load(void *opaque, int version_id)
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{
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SLAVIO_INTCTLState *s = opaque;
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slavio_check_interrupts(s, 0);
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return 0;
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}
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static const VMStateDescription vmstate_intctl_cpu = {
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.name ="slavio_intctl_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_intctl = {
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.name ="slavio_intctl",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_intctl_post_load,
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.fields = (VMStateField []) {
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VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
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vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
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VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
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VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
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VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void slavio_intctl_reset(DeviceState *d)
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{
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SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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s->slaves[i].intreg_pending = 0;
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s->slaves[i].irl_out = 0;
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}
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s->intregm_disabled = ~MASTER_IRQ_MASK;
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s->intregm_pending = 0;
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s->target_cpu = 0;
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slavio_check_interrupts(s, 0);
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}
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static int slavio_intctl_init1(SysBusDevice *dev)
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{
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SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
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int io_memory;
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unsigned int i, j;
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qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
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io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
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slavio_intctlm_mem_write, s);
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sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
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for (i = 0; i < MAX_CPUS; i++) {
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for (j = 0; j < MAX_PILS; j++) {
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sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
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}
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io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
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slavio_intctl_mem_write,
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&s->slaves[i]);
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sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
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s->slaves[i].cpu = i;
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s->slaves[i].master = s;
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}
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return 0;
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}
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static SysBusDeviceInfo slavio_intctl_info = {
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.init = slavio_intctl_init1,
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.qdev.name = "slavio_intctl",
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.qdev.size = sizeof(SLAVIO_INTCTLState),
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.qdev.vmsd = &vmstate_intctl,
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.qdev.reset = slavio_intctl_reset,
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};
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static void slavio_intctl_register_devices(void)
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{
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sysbus_register_withprop(&slavio_intctl_info);
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}
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device_init(slavio_intctl_register_devices)
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