Richard Henderson b5cf742841 accel/tcg: Remove TranslatorOps.breakpoint_check ... The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-07-21 07:47:05 -10:00
..
insn_trans	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
arch_dump.c
bitmanip_helper.c	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
cpu_bits.h	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
cpu_helper.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
cpu.h	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
csr.c	target/riscv: hardwire bits in hideleg and hedeleg	2021-07-15 08:56:00 +10:00
fpu_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00
gdbstub.c	target/riscv: gdbstub: Fix dynamic CSR XML generation	2021-06-24 05:00:12 -07:00
helper.h	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
instmap.h
internals.h
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c	target/riscv: Remove the hardcoded SATP_MODE macro	2021-05-11 20:02:07 +10:00
op_helper.c	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
pmp.c	target/riscv: pmp: Fix some typos	2021-07-15 08:56:00 +10:00
pmp.h
trace-events
trace.h
translate.c	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00
vector_helper.c	target/riscv: Consolidate RV32/64 32-bit instructions	2021-05-11 20:02:07 +10:00