1ab5f75cf0
Avoid scheduling DMA processing when all channels are stopped or at end-of-list. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5720 c046a42c-6fe2-441c-8c8c-71466251a162
780 lines
22 KiB
C
780 lines
22 KiB
C
/*
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* QEMU ETRAX DMA Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <sys/time.h>
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#include "hw.h"
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#include "qemu-common.h"
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#include "sysemu.h"
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#include "etraxfs_dma.h"
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#define D(x)
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#define RW_DATA 0x0
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#define RW_SAVED_DATA 0x58
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#define RW_SAVED_DATA_BUF 0x5c
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#define RW_GROUP 0x60
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#define RW_GROUP_DOWN 0x7c
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#define RW_CMD 0x80
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#define RW_CFG 0x84
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#define RW_STAT 0x88
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#define RW_INTR_MASK 0x8c
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#define RW_ACK_INTR 0x90
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#define R_INTR 0x94
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#define R_MASKED_INTR 0x98
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#define RW_STREAM_CMD 0x9c
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#define DMA_REG_MAX 0x100
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group {
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struct dma_descr_group *next;
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unsigned eol : 1;
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unsigned tol : 1;
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unsigned bol : 1;
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unsigned : 1;
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unsigned intr : 1;
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unsigned : 2;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md : 16;
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down;
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} dma_descr_group;
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context {
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struct dma_descr_context *next;
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unsigned eol : 1;
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unsigned : 3;
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unsigned intr : 1;
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unsigned : 1;
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unsigned store_mode : 1;
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unsigned en : 1;
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unsigned : 7;
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unsigned dis : 1;
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unsigned md0 : 16;
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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struct dma_descr_data *saved_data;
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char *saved_data_buf;
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} dma_descr_context;
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data {
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struct dma_descr_data *next;
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char *buf;
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unsigned eol : 1;
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unsigned : 2;
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unsigned out_eop : 1;
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unsigned intr : 1;
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unsigned wait : 1;
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unsigned : 2;
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unsigned : 3;
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unsigned in_eop : 1;
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unsigned : 4;
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unsigned md : 16;
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char *after;
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} dma_descr_data;
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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};
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enum dma_ch_state
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{
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RST = 1,
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STOPPED = 2,
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RUNNING = 4
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};
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struct fs_dma_channel
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{
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int regmap;
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qemu_irq *irq;
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struct etraxfs_dma_client *client;
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/* Internal status. */
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int stream_cmd_src;
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enum dma_ch_state state;
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unsigned int input : 1;
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unsigned int eol : 1;
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struct dma_descr_group current_g;
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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uint32_t regs[DMA_REG_MAX];
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};
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struct fs_dma_ctrl
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{
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CPUState *env;
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target_phys_addr_t base;
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int nr_channels;
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struct fs_dma_channel *channels;
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QEMUBH *bh;
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};
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static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
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{
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return ctrl->channels[c].regs[reg];
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}
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static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
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{
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return channel_reg(ctrl, c, RW_CFG) & 2;
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}
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static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
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{
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return (channel_reg(ctrl, c, RW_CFG) & 1)
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&& ctrl->channels[c].client;
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}
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static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
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{
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/* Every channel has a 0x2000 ctrl register map. */
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return (addr - base) >> 13;
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}
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#ifdef USE_THIS_DEAD_CODE
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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}
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static void dump_c(int ch, struct dma_descr_context *c)
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", c->next);
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printf("saved_data=%p\n", c->saved_data);
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printf("saved_data_buf=%p\n", c->saved_data_buf);
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printf("eol=%x\n", (uint32_t) c->eol);
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}
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static void dump_d(int ch, struct dma_descr_data *d)
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{
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%p\n", d->next);
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printf("buf=%p\n", d->buf);
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printf("after=%p\n", d->after);
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printf("intr=%x\n", (uint32_t) d->intr);
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printf("out_eop=%x\n", (uint32_t) d->out_eop);
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printf("in_eop=%x\n", (uint32_t) d->in_eop);
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printf("eol=%x\n", (uint32_t) d->eol);
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}
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#endif
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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D(dump_c(c, &ctrl->channels[c].current_c));
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/* I guess this should update the current pos. */
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
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}
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d));
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ctrl->channels[c].regs[RW_DATA] = addr;
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}
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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D(dump_d(c, &ctrl->channels[c].current_d));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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}
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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}
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
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{
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/* FIXME: */
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}
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static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
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{
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if (ctrl->channels[c].client)
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{
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ctrl->channels[c].eol = 0;
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ctrl->channels[c].state = RUNNING;
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} else
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printf("WARNING: starting DMA ch %d with no client\n", c);
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qemu_bh_schedule_idle(ctrl->bh);
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}
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static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
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{
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if (!channel_en(ctrl, c)
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|| channel_stopped(ctrl, c)
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|| ctrl->channels[c].state != RUNNING
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/* Only reload the current data descriptor if it has eol set. */
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|| !ctrl->channels[c].current_d.eol) {
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D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
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c, ctrl->channels[c].state,
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channel_stopped(ctrl, c),
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channel_en(ctrl,c),
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ctrl->channels[c].eol));
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D(dump_d(c, &ctrl->channels[c].current_d));
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return;
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}
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/* Reload the current descriptor. */
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channel_load_d(ctrl, c);
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %p\n", c,
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ctrl->channels[c].current_d.next));
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
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channel_load_d(ctrl, c);
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channel_start(ctrl, c);
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}
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
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}
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
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{
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unsigned int cmd = v & ((1 << 10) - 1);
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D(printf("%s ch=%d cmd=%x\n",
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__func__, c, cmd));
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if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c);
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if (cmd & regk_dma_burst)
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channel_start(ctrl, c);
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}
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if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c);
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channel_start(ctrl, c);
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}
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}
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static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
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{
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D(printf("%s %d\n", __func__, c));
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ctrl->channels[c].regs[R_INTR] &=
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~(ctrl->channels[c].regs[RW_ACK_INTR]);
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ctrl->channels[c].regs[R_MASKED_INTR] =
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ctrl->channels[c].regs[R_INTR]
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& ctrl->channels[c].regs[RW_INTR_MASK];
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D(printf("%s: chan=%d masked_intr=%x\n", __func__,
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c,
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ctrl->channels[c].regs[R_MASKED_INTR]));
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if (ctrl->channels[c].regs[R_MASKED_INTR])
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qemu_irq_raise(ctrl->channels[c].irq[0]);
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else
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qemu_irq_lower(ctrl->channels[c].irq[0]);
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}
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static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
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{
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uint32_t len;
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uint32_t saved_data_buf;
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unsigned char buf[2 * 1024];
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if (ctrl->channels[c].eol)
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return 0;
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do {
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saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
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D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
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c,
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(uint32_t)ctrl->channels[c].current_d.buf,
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(uint32_t)ctrl->channels[c].current_d.after,
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saved_data_buf));
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len = (uint32_t)(unsigned long)
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ctrl->channels[c].current_d.after;
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len -= saved_data_buf;
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if (len > sizeof buf)
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len = sizeof buf;
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cpu_physical_memory_read (saved_data_buf, buf, len);
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D(printf("channel %d pushes %x %u bytes\n", c,
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saved_data_buf, len));
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if (ctrl->channels[c].client->client.push)
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ctrl->channels[c].client->client.push(
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ctrl->channels[c].client->client.opaque,
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buf, len);
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else
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printf("WARNING: DMA ch%d dataloss,"
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" no attached client.\n", c);
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saved_data_buf += len;
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if (saved_data_buf == (uint32_t)(unsigned long)
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ctrl->channels[c].current_d.after) {
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/* Done. Step to next. */
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if (ctrl->channels[c].current_d.out_eop) {
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/* TODO: signal eop to the client. */
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D(printf("signal eop\n"));
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}
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if (ctrl->channels[c].current_d.intr) {
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/* TODO: signal eop to the client. */
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/* data intr. */
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D(printf("signal intr\n"));
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ctrl->channels[c].regs[R_INTR] |= (1 << 2);
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channel_update_irq(ctrl, c);
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}
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if (ctrl->channels[c].current_d.eol) {
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D(printf("channel %d EOL\n", c));
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ctrl->channels[c].eol = 1;
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/* Mark the context as disabled. */
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ctrl->channels[c].current_c.dis = 1;
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channel_store_c(ctrl, c);
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channel_stop(ctrl, c);
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} else {
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t)(unsigned long)ctrl->
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channels[c].current_d.next;
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/* Load new descriptor. */
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channel_load_d(ctrl, c);
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saved_data_buf = (uint32_t)(unsigned long)
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ctrl->channels[c].current_d.buf;
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}
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channel_store_d(ctrl, c);
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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saved_data_buf;
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D(dump_d(c, &ctrl->channels[c].current_d));
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}
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
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} while (!ctrl->channels[c].eol);
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return 1;
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}
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static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
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unsigned char *buf, int buflen, int eop)
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{
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uint32_t len;
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uint32_t saved_data_buf;
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if (ctrl->channels[c].eol == 1)
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return 0;
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saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
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len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
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len -= saved_data_buf;
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if (len > buflen)
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len = buflen;
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cpu_physical_memory_write (saved_data_buf, buf, len);
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saved_data_buf += len;
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if (saved_data_buf ==
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.after
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|| eop) {
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uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
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D(printf("in dscr end len=%d\n",
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ctrl->channels[c].current_d.after
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- ctrl->channels[c].current_d.buf));
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ctrl->channels[c].current_d.after =
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(void *)(unsigned long) saved_data_buf;
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/* Done. Step to next. */
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if (ctrl->channels[c].current_d.intr) {
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/* TODO: signal eop to the client. */
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/* data intr. */
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ctrl->channels[c].regs[R_INTR] |= 3;
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}
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if (eop) {
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ctrl->channels[c].current_d.in_eop = 1;
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ctrl->channels[c].regs[R_INTR] |= 8;
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}
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if (r_intr != ctrl->channels[c].regs[R_INTR])
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channel_update_irq(ctrl, c);
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channel_store_d(ctrl, c);
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D(dump_d(c, &ctrl->channels[c].current_d));
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if (ctrl->channels[c].current_d.eol) {
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D(printf("channel %d EOL\n", c));
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ctrl->channels[c].eol = 1;
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/* Mark the context as disabled. */
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ctrl->channels[c].current_c.dis = 1;
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channel_store_c(ctrl, c);
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channel_stop(ctrl, c);
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} else {
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t)(unsigned long)ctrl->
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channels[c].current_d.next;
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/* Load new descriptor. */
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channel_load_d(ctrl, c);
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saved_data_buf = (uint32_t)(unsigned long)
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ctrl->channels[c].current_d.buf;
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}
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}
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
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return len;
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}
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static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
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{
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if (ctrl->channels[c].client->client.pull) {
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ctrl->channels[c].client->client.pull(
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ctrl->channels[c].client->client.opaque);
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return 1;
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} else
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return 0;
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}
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static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
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{
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struct fs_dma_ctrl *ctrl = opaque;
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CPUState *env = ctrl->env;
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cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
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addr);
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return 0;
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}
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static uint32_t
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dma_readl (void *opaque, target_phys_addr_t addr)
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{
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struct fs_dma_ctrl *ctrl = opaque;
|
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int c;
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uint32_t r = 0;
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|
|
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/* Make addr relative to this instances base. */
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c = fs_channel(ctrl->base, addr);
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addr &= 0x1fff;
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|
switch (addr)
|
|
{
|
|
case RW_STAT:
|
|
r = ctrl->channels[c].state & 7;
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|
r |= ctrl->channels[c].eol << 5;
|
|
r |= ctrl->channels[c].stream_cmd_src << 8;
|
|
break;
|
|
|
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default:
|
|
r = ctrl->channels[c].regs[addr];
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|
D(printf ("%s c=%d addr=%x\n",
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|
__func__, c, addr));
|
|
break;
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|
}
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|
return r;
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|
}
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|
|
|
static void
|
|
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = opaque;
|
|
CPUState *env = ctrl->env;
|
|
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
|
|
addr);
|
|
}
|
|
|
|
static void
|
|
dma_update_state(struct fs_dma_ctrl *ctrl, int c)
|
|
{
|
|
if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
|
|
if (ctrl->channels[c].regs[RW_CFG] & 2)
|
|
ctrl->channels[c].state = STOPPED;
|
|
if (!(ctrl->channels[c].regs[RW_CFG] & 1))
|
|
ctrl->channels[c].state = RST;
|
|
}
|
|
}
|
|
|
|
static void
|
|
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = opaque;
|
|
int c;
|
|
|
|
/* Make addr relative to this instances base. */
|
|
c = fs_channel(ctrl->base, addr);
|
|
addr &= 0x1fff;
|
|
switch (addr)
|
|
{
|
|
case RW_DATA:
|
|
ctrl->channels[c].regs[addr] = value;
|
|
break;
|
|
|
|
case RW_CFG:
|
|
ctrl->channels[c].regs[addr] = value;
|
|
dma_update_state(ctrl, c);
|
|
break;
|
|
case RW_CMD:
|
|
/* continue. */
|
|
if (value & ~1)
|
|
printf("Invalid store to ch=%d RW_CMD %x\n",
|
|
c, value);
|
|
ctrl->channels[c].regs[addr] = value;
|
|
channel_continue(ctrl, c);
|
|
break;
|
|
|
|
case RW_SAVED_DATA:
|
|
case RW_SAVED_DATA_BUF:
|
|
case RW_GROUP:
|
|
case RW_GROUP_DOWN:
|
|
ctrl->channels[c].regs[addr] = value;
|
|
break;
|
|
|
|
case RW_ACK_INTR:
|
|
case RW_INTR_MASK:
|
|
ctrl->channels[c].regs[addr] = value;
|
|
channel_update_irq(ctrl, c);
|
|
if (addr == RW_ACK_INTR)
|
|
ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
|
break;
|
|
|
|
case RW_STREAM_CMD:
|
|
if (value & ~1023)
|
|
printf("Invalid store to ch=%d "
|
|
"RW_STREAMCMD %x\n",
|
|
c, value);
|
|
ctrl->channels[c].regs[addr] = value;
|
|
D(printf("stream_cmd ch=%d\n", c));
|
|
channel_stream_cmd(ctrl, c, value);
|
|
break;
|
|
|
|
default:
|
|
D(printf ("%s c=%d %x %x\n", __func__, c, addr));
|
|
break;
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc *dma_read[] = {
|
|
&dma_rinvalid,
|
|
&dma_rinvalid,
|
|
&dma_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc *dma_write[] = {
|
|
&dma_winvalid,
|
|
&dma_winvalid,
|
|
&dma_writel,
|
|
};
|
|
|
|
static int etraxfs_dmac_run(void *opaque)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = opaque;
|
|
int i;
|
|
int p = 0;
|
|
|
|
for (i = 0;
|
|
i < ctrl->nr_channels;
|
|
i++)
|
|
{
|
|
if (ctrl->channels[i].state == RUNNING)
|
|
{
|
|
if (ctrl->channels[i].input) {
|
|
p += channel_in_run(ctrl, i);
|
|
} else {
|
|
p += channel_out_run(ctrl, i);
|
|
}
|
|
}
|
|
}
|
|
return p;
|
|
}
|
|
|
|
int etraxfs_dmac_input(struct etraxfs_dma_client *client,
|
|
void *buf, int len, int eop)
|
|
{
|
|
return channel_in_process(client->ctrl, client->channel,
|
|
buf, len, eop);
|
|
}
|
|
|
|
/* Connect an IRQ line with a channel. */
|
|
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = opaque;
|
|
ctrl->channels[c].irq = line;
|
|
ctrl->channels[c].input = input;
|
|
}
|
|
|
|
void etraxfs_dmac_connect_client(void *opaque, int c,
|
|
struct etraxfs_dma_client *cl)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = opaque;
|
|
cl->ctrl = ctrl;
|
|
cl->channel = c;
|
|
ctrl->channels[c].client = cl;
|
|
}
|
|
|
|
|
|
static void DMA_run(void *opaque)
|
|
{
|
|
struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
|
int p = 1;
|
|
|
|
if (vm_running)
|
|
p = etraxfs_dmac_run(etraxfs_dmac);
|
|
|
|
if (p)
|
|
qemu_bh_schedule_idle(etraxfs_dmac->bh);
|
|
}
|
|
|
|
void *etraxfs_dmac_init(CPUState *env,
|
|
target_phys_addr_t base, int nr_channels)
|
|
{
|
|
struct fs_dma_ctrl *ctrl = NULL;
|
|
int i;
|
|
|
|
ctrl = qemu_mallocz(sizeof *ctrl);
|
|
if (!ctrl)
|
|
return NULL;
|
|
|
|
ctrl->bh = qemu_bh_new(DMA_run, ctrl);
|
|
|
|
ctrl->base = base;
|
|
ctrl->env = env;
|
|
ctrl->nr_channels = nr_channels;
|
|
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
|
|
if (!ctrl->channels)
|
|
goto err;
|
|
|
|
for (i = 0; i < nr_channels; i++)
|
|
{
|
|
ctrl->channels[i].regmap = cpu_register_io_memory(0,
|
|
dma_read,
|
|
dma_write,
|
|
ctrl);
|
|
cpu_register_physical_memory (base + i * 0x2000,
|
|
sizeof ctrl->channels[i].regs,
|
|
ctrl->channels[i].regmap);
|
|
}
|
|
|
|
return ctrl;
|
|
err:
|
|
qemu_free(ctrl->channels);
|
|
qemu_free(ctrl);
|
|
return NULL;
|
|
}
|