8063396bf3
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/*
|
|
* QEMU RISC-V Hart Array interface
|
|
*
|
|
* Copyright (c) 2017 SiFive, Inc.
|
|
*
|
|
* Holds the state of a heterogenous array of RISC-V harts
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef HW_RISCV_HART_H
|
|
#define HW_RISCV_HART_H
|
|
|
|
#include "hw/sysbus.h"
|
|
#include "target/riscv/cpu.h"
|
|
#include "qom/object.h"
|
|
|
|
#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
|
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_HART_ARRAY)
|
|
|
|
struct RISCVHartArrayState {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
uint32_t num_harts;
|
|
uint32_t hartid_base;
|
|
char *cpu_type;
|
|
uint64_t resetvec;
|
|
RISCVCPU *harts;
|
|
};
|
|
|
|
#endif
|