1da79ecc7a
Avoid using a magic number (4) everywhere for the number of chip selects supported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-id: 20210129132323.30946-2-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
108 lines
2.6 KiB
C
108 lines
2.6 KiB
C
/*
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* IMX SPI Controller
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*
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* Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef IMX_SPI_H
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#define IMX_SPI_H
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#include "hw/sysbus.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/bitops.h"
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#include "qemu/fifo32.h"
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#include "qom/object.h"
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#define ECSPI_FIFO_SIZE 64
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#define ECSPI_RXDATA 0
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#define ECSPI_TXDATA 1
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#define ECSPI_CONREG 2
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#define ECSPI_CONFIGREG 3
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#define ECSPI_INTREG 4
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#define ECSPI_DMAREG 5
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#define ECSPI_STATREG 6
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#define ECSPI_PERIODREG 7
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#define ECSPI_TESTREG 8
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#define ECSPI_MSGDATA 16
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#define ECSPI_MAX 17
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/* ECSPI_CONREG */
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#define ECSPI_CONREG_EN (1 << 0)
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#define ECSPI_CONREG_HT (1 << 1)
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#define ECSPI_CONREG_XCH (1 << 2)
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#define ECSPI_CONREG_SMC (1 << 3)
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#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4
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#define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4
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#define ECSPI_CONREG_DRCTL_SHIFT 16
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#define ECSPI_CONREG_DRCTL_LENGTH 2
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#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18
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#define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2
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#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20
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#define ECSPI_CONREG_BURST_LENGTH_LENGTH 12
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/* ECSPI_CONFIGREG */
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#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8
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#define ECSPI_CONFIGREG_SS_CTL_LENGTH 4
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/* ECSPI_INTREG */
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#define ECSPI_INTREG_TEEN (1 << 0)
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#define ECSPI_INTREG_TDREN (1 << 1)
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#define ECSPI_INTREG_TFEN (1 << 2)
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#define ECSPI_INTREG_RREN (1 << 3)
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#define ECSPI_INTREG_RDREN (1 << 4)
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#define ECSPI_INTREG_RFEN (1 << 5)
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#define ECSPI_INTREG_ROEN (1 << 6)
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#define ECSPI_INTREG_TCEN (1 << 7)
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/* ECSPI_DMAREG */
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#define ECSPI_DMAREG_RXTDEN (1 << 31)
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#define ECSPI_DMAREG_RXDEN (1 << 23)
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#define ECSPI_DMAREG_TEDEN (1 << 7)
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#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16
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#define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6
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/* ECSPI_STATREG */
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#define ECSPI_STATREG_TE (1 << 0)
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#define ECSPI_STATREG_TDR (1 << 1)
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#define ECSPI_STATREG_TF (1 << 2)
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#define ECSPI_STATREG_RR (1 << 3)
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#define ECSPI_STATREG_RDR (1 << 4)
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#define ECSPI_STATREG_RF (1 << 5)
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#define ECSPI_STATREG_RO (1 << 6)
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#define ECSPI_STATREG_TC (1 << 7)
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#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
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/* number of chip selects supported */
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#define ECSPI_NUM_CS 4
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#define TYPE_IMX_SPI "imx.spi"
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OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
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struct IMXSPIState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq cs_lines[ECSPI_NUM_CS];
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SSIBus *bus;
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uint32_t regs[ECSPI_MAX];
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Fifo32 rx_fifo;
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Fifo32 tx_fifo;
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int16_t burst_length;
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};
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#endif /* IMX_SPI_H */
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