eb8b0224fc
For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND. Otherwise, use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
189 lines
7.3 KiB
C
189 lines
7.3 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef S390_TCG_TARGET_H
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#define S390_TCG_TARGET_H
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#define TCG_TARGET_INSN_UNIT_SIZE 2
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
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/* We have a +- 4GB range on the branches; leave some slop. */
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#define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB)
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typedef enum TCGReg {
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TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
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TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
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TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
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TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
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TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
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TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
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TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
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TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
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TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
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TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
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TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
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TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
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TCG_AREG0 = TCG_REG_R10,
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TCG_REG_CALL_STACK = TCG_REG_R15
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} TCGReg;
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#define TCG_TARGET_NB_REGS 64
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/* A list of relevant facilities used by this translator. Some of these
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are required for proper operation, and these are checked at startup. */
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#define FACILITY_ZARCH_ACTIVE 2
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#define FACILITY_LONG_DISP 18
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#define FACILITY_EXT_IMM 21
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#define FACILITY_GEN_INST_EXT 34
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#define FACILITY_LOAD_ON_COND 45
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#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
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#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
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#define FACILITY_LOAD_ON_COND2 53
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#define FACILITY_VECTOR 129
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#define FACILITY_VECTOR_ENH1 135
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extern uint64_t s390_facilities[3];
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#define HAVE_FACILITY(X) \
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((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
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/* optional instructions */
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#define TCG_TARGET_HAS_div2_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 0
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 0
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 0
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT)
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#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT)
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_extrl_i64_i32 0
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#define TCG_TARGET_HAS_extrh_i64_i32 0
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#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT)
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_div2_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 0
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM)
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT)
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#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT)
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_muluh_i64 0
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#define TCG_TARGET_HAS_mulsh_i64 0
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#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR)
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#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1)
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#define TCG_TARGET_HAS_nand_vec HAVE_FACILITY(VECTOR_ENH1)
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#define TCG_TARGET_HAS_nor_vec 1
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#define TCG_TARGET_HAS_eqv_vec HAVE_FACILITY(VECTOR_ENH1)
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_roti_vec 1
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#define TCG_TARGET_HAS_rots_vec 1
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#define TCG_TARGET_HAS_rotv_vec 1
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 0
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_STACK_OFFSET 160
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_HAS_MEMORY_BSWAP 1
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#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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uintptr_t jmp_rw, uintptr_t addr)
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{
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/* patch the branch destination */
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intptr_t disp = addr - (jmp_rx - 2);
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qatomic_set((int32_t *)jmp_rw, disp / 2);
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/* no need to flush icache explicitly */
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}
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif
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