Stephen Long cf32744981 target/arm: Implement SVE2 gather load insns ... Add decoding logic for SVE2 64-bit/32-bit gather non-temporal load insns. 64-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1SW * LDNT1W (vector plus scalar) * LDNT1D (vector plus scalar) 32-bit * LDNT1SB * LDNT1B (vector plus scalar) * LDNT1SH * LDNT1H (vector plus scalar) * LDNT1W (vector plus scalar) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-46-richard.henderson@linaro.org Message-Id: <20200422152343.12493-1-steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-05-25 16:01:44 +01:00
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alpha
arm	target/arm: Implement SVE2 gather load insns	2021-05-25 16:01:44 +01:00
avr
cris
hexagon
hppa
i386	s390x fixes and cleanups; also related fixes in xtensa,	2021-05-20 18:42:00 +01:00
m68k
microblaze
mips
nios2
openrisc
ppc	target/ppc: Remove type argument for mmubooke206_get_physical_address	2021-05-19 12:52:07 +10:00
riscv
rx
s390x	target/s390x: Fix translation exception on illegal instruction	2021-05-20 14:19:30 +02:00
sh4
sparc
tricore
xtensa	target/xtensa: clean up unaligned access	2021-05-20 13:02:58 -07:00
meson.build