Bin Meng 495134b75c hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 ... Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-06-19 08:25:27 -07:00
..
alpha	accel/tcg: Relax va restrictions on 64-bit guests	2020-05-15 15:25:16 +01:00
arm	target/arm/cpu: adjust virtual time for all KVM arm cpus	2020-06-16 10:32:29 +01:00
cris
hppa	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
i386	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	2020-06-15 22:06:04 +02:00
lm32
m68k	target/m68k: implement opcode fetoxm1	2020-06-02 13:59:02 +02:00
microblaze	target/microblaze: monitor: Increase the number of registers reported	2020-05-14 16:01:02 +02:00
mips	target/mips: msa: Split helpers for MULV.<B|H|W|D>	2020-06-15 20:51:04 +02:00
moxie
nios2
openrisc	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00
ppc	target/ppc: Restrict PPCVirtualHypervisorClass to system-mode	2020-06-12 11:12:45 -04:00
riscv	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	2020-06-19 08:25:27 -07:00
rx
s390x	vfio-ccw: Add support for the schib region	2020-06-18 12:13:54 +02:00
sh4
sparc	target/sparc/int32_helper: Extract and use excp_name_str()	2020-06-09 09:21:10 +02:00
tilegx
tricore	target/tricore: Implement gdbstub	2020-06-01 16:55:13 +02:00
unicore32	target/unicore32: Prefer qemu_semihosting_log_out() over curses	2020-06-09 19:58:53 +02:00
xtensa	softfloat: Name compare relation enum	2020-05-19 08:41:45 -07:00