OpenE2K/qemu-e2k
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cf7beda507
qemu-e2k/target
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Christophe Lyon cf7beda507 target/arm: Add support for cortex-m7 CPU 
This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
..
alpha target/alpha: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
arm target/arm: Add support for cortex-m7 CPU 2019-12-16 10:46:34 +00:00
cris cputlb: ensure _cmmu helper functions follow the naming standard 2019-10-28 15:12:38 +00:00
hppa target/hppa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
i386 target/i386: disable VMX features if nested=0 2019-12-06 12:35:40 +01:00
lm32
m68k target/m68k: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
microblaze target/microblaze: Plug temp leak around eval_cond_jmp() 2019-11-12 16:35:26 +01:00
mips target/mips: Refactor handling of vector compare 'less than' (signed) instructions 2019-10-25 18:37:01 +02:00
moxie
nios2
openrisc target/openrisc: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
ppc spapr/kvm: Set default cpu model for all machine classes 2019-11-18 11:50:39 +01:00
riscv target/riscv: Remove atomic accesses to MIP CSR 2019-11-14 09:53:28 -08:00
s390x s390x/kvm: Set default cpu model for all machine classes 2019-10-21 18:03:08 +02:00
sh4 target/sh4: fetch code with translator_ld 2019-10-28 15:12:38 +00:00
sparc target/sparc: Define an enumeration for accessing env->regwptr 2019-11-06 13:35:25 +01:00
tilegx tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
tricore tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
unicore32
xtensa target/xtensa: fetch code with translator_ld 2019-10-28 15:12:38 +00:00