4a129ccdf2
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201023122633.19466-1-chetan4windows@gmail.com> [PMD: Added hw/mips/ prefix in subject] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* Xilinx PCIe host controller emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_XILINX_PCIE_H
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#define HW_XILINX_PCIE_H
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie_host.h"
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#include "qom/object.h"
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#define TYPE_XILINX_PCIE_HOST "xilinx-pcie-host"
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OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIEHost, XILINX_PCIE_HOST)
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#define TYPE_XILINX_PCIE_ROOT "xilinx-pcie-root"
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OBJECT_DECLARE_SIMPLE_TYPE(XilinxPCIERoot, XILINX_PCIE_ROOT)
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struct XilinxPCIERoot {
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PCIBridge parent_obj;
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};
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typedef struct XilinxPCIEInt {
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uint32_t fifo_reg1;
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uint32_t fifo_reg2;
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} XilinxPCIEInt;
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struct XilinxPCIEHost {
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PCIExpressHost parent_obj;
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char name[16];
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uint32_t bus_nr;
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uint64_t cfg_base, cfg_size;
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uint64_t mmio_base, mmio_size;
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bool link_up;
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qemu_irq irq;
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MemoryRegion mmio, io;
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XilinxPCIERoot root;
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uint32_t intr;
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uint32_t intr_mask;
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XilinxPCIEInt intr_fifo[16];
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unsigned int intr_fifo_r, intr_fifo_w;
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uint32_t rpscr;
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};
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#endif /* HW_XILINX_PCIE_H */
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