Alexandre Mergnat cfad709bce target/riscv: Fix pmp NA4 implementation ... The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200706084550.24117-1-amergnat@baylibre.com Message-Id: <20200706084550.24117-1-amergnat@baylibre.com> [ Changes by AF: - Improve the commit title and message ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-07-13 17:25:37 -07:00
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insn_trans	target/riscv: fix return value of do_opivx_widen()	2020-07-13 17:25:37 -07:00
cpu_bits.h	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2020-06-19 08:24:07 -07:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: configure and turn on vector extension from command line	2020-07-02 09:19:34 -07:00
cpu.h	target/riscv: fix vill bit index in vtype register	2020-07-13 17:25:37 -07:00
csr.c	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
fpu_helper.c	target/riscv: vector floating-point classify instructions	2020-07-02 09:19:33 -07:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
insn32.decode	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
instmap.h
internals.h	target/riscv: integer scalar move instruction	2020-07-02 09:19:33 -07:00
Makefile.objs	target/riscv: add vector configure instruction	2020-07-02 09:19:32 -07:00
monitor.c	target/riscv: Drop support for ISA spec version 1.09.1	2020-06-03 09:11:51 -07:00
op_helper.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
pmp.c	target/riscv: Fix pmp NA4 implementation	2020-07-13 17:25:37 -07:00
pmp.h
trace-events
translate.c	target/riscv: add vector stride load and store instructions	2020-07-02 09:19:32 -07:00
vector_helper.c	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00