dccb92b5ca
A difference between sbsa platform and the virt platform is PSCI is handled by ARM-TF in the sbsa platform. This means that the PSCI code there needs to communicate some of the platform power changes down to the qemu code for things like shutdown/reset control. Space has been left to extend the EC if we find other use cases in future where ARM-TF and qemu need to communicate. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20200826141952.136164-2-graeme@nuviainc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* ARM SBSA Reference Platform Embedded Controller
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*
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* A device to allow PSCI running in the secure side of sbsa-ref machine
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* to communicate platform power states to qemu.
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*
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* Copyright (c) 2020 Nuvia Inc
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* Written by Graeme Gregory <graeme@nuviainc.com>
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*
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* SPDX-License-Identifer: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "sysemu/runstate.h"
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typedef struct {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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} SECUREECState;
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#define TYPE_SBSA_EC "sbsa-ec"
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#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
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enum sbsa_ec_powerstates {
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SBSA_EC_CMD_POWEROFF = 0x01,
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SBSA_EC_CMD_REBOOT = 0x02,
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};
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static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
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{
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/* No use for this currently */
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qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: no readable registers");
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return 0;
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}
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static void sbsa_ec_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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if (offset == 0) { /* PSCI machine power command register */
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switch (value) {
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case SBSA_EC_CMD_POWEROFF:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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break;
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case SBSA_EC_CMD_REBOOT:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"sbsa-ec: unknown power command");
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: unknown EC register");
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}
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}
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static const MemoryRegionOps sbsa_ec_ops = {
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.read = sbsa_ec_read,
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.write = sbsa_ec_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void sbsa_ec_init(Object *obj)
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{
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SECUREECState *s = SECURE_EC(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
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0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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}
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static void sbsa_ec_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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/* No vmstate or reset required: device has no internal state */
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dc->user_creatable = false;
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}
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static const TypeInfo sbsa_ec_info = {
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.name = TYPE_SBSA_EC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SECUREECState),
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.instance_init = sbsa_ec_init,
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.class_init = sbsa_ec_class_init,
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};
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static void sbsa_ec_register_type(void)
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{
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type_register_static(&sbsa_ec_info);
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}
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type_init(sbsa_ec_register_type);
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