Philippe Mathieu-Daudé d0bec217ee target/mips/cpu: Make cp0_count_rate a property ...

Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>

2020-10-17 11:13:15 +02:00

..

cp0_helper.c

target/mips: Move cpu_mips_get_random() with CP0 helpers

2020-10-17 11:13:15 +02:00

cp0_timer.c

target/mips: Move cp0_count_ns to CPUMIPSState

2020-10-17 11:13:15 +02:00

cpu-param.h

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cpu-qom.h

qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros

2020-09-18 14:12:32 -04:00

cpu.c

target/mips/cpu: Make cp0_count_rate a property

2020-10-17 11:13:15 +02:00

cpu.h

target/mips/cpu: Make cp0_count_rate a property

2020-10-17 11:13:15 +02:00

dsp_helper.c

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fpu_helper.c

target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>

2020-10-17 11:09:33 +02:00

gdbstub.c

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helper.c

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helper.h

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internal.h

target/mips: Move cpu_mips_get_random() with CP0 helpers

2020-10-17 11:13:15 +02:00

kvm_mips.h

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kvm.c

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lmmi_helper.c

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machine.c

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meson.build

meson: target

2020-08-21 06:30:35 -04:00

mips-defs.h

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mips-semi.c

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msa_helper.c

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op_helper.c

target/mips/op_helper: Log unimplemented cache opcode

2020-10-17 11:13:15 +02:00

TODO

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trace-events

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trace.h

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translate_init.c.inc

target/mips: Fix some comment spelling errors

2020-10-17 11:08:42 +02:00

translate.c

target/mips: Add loongson-ext lsdc2 group of instructions

2020-10-17 11:13:15 +02:00