Atish Patra 1a475d39ef RISC-V: Place DTB at 3GB boundary instead of 4GB ... Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is lesser. However, Linux kernel can address only 1GB of memory for RV32. Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address). As a result, it can not process DT and panic if opensbi dynamic firmware is used. While at it, place the DTB further away to avoid in memory placement issues in future. Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower. Fixes: 66b1205bc5 ("RISC-V: Copy the fdt in dram instead of ROM") Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Message-id: 20210107091127.3407870-1-atish.patra@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-01-16 10:57:21 -08:00
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Kconfig	hw/riscv: microchip_pfsoc: Connect the SYSREG module	2020-11-03 07:17:23 -08:00
boot.c	RISC-V: Place DTB at 3GB boundary instead of 4GB	2021-01-16 10:57:21 -08:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: add QSPI NOR flash	2020-12-17 21:56:43 -08:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	riscv/opentitan: Update the OpenTitan memory layout	2020-12-17 21:56:44 -08:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
sifive_u.c	hw/riscv: Use the CPU to determine if 32-bit	2020-12-17 21:56:44 -08:00
spike.c	hw/riscv: Use the CPU to determine if 32-bit	2020-12-17 21:56:44 -08:00
virt.c	hw/riscv: Use the CPU to determine if 32-bit	2020-12-17 21:56:44 -08:00