qemu-e2k/target
Daniel Henrique Barboza d167a2247e target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]
Every property in riscv_cpu_options[] will be migrated to
riscv_cpu_properties[]. This will make their default values init
earlier, allowing cpu_init() functions to overwrite them. We'll also
implement common getters and setters that both accelerators will use,
allowing them to share validations that TCG is doing.

At the same time, some options (namely 'vlen', 'elen' and the cache
blocksizes) need a way of tracking if the user set a value for them.
This is benign for TCG since the cost of always validating these values
are small, but for KVM we need syscalls to read the host values to make
the validations, thus knowing whether the user didn't touch the values
makes a difference.

We'll track user setting for these properties using a hash, like we do
in the TCG driver. All riscv cpu options will update this hash in case
the user sets it. The KVM driver will use this hash to minimize the
amount of syscalls done.

For now, both 'pmu-mask' and 'pmu-num' shouldn't be changed for vendor
CPUs. The existing setter for 'pmu-num' is changed to add this
restriction. New getters and setters are required for 'pmu-mask'

While we're at it, add a 'static' modifier to 'prop_pmu_num' since we're
not exporting it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Message-ID: <20240105230546.265053-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09 10:44:22 +10:00
..
alpha target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero 2024-02-03 23:43:50 +00:00
arm tests/tcg: Fix multiarch/gdbstub/prot-none.py 2024-02-03 13:31:45 +00:00
avr include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
cris include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
hexagon include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
hppa include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
i386 include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
loongarch include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
m68k target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond 2024-02-03 23:43:50 +00:00
microblaze include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
mips include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
nios2 include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
openrisc include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
ppc target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules 2024-02-05 14:21:21 +01:00
riscv target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] 2024-02-09 10:44:22 +10:00
rx include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
s390x tcg: Introduce TCG_COND_TST{EQ,NE} 2024-02-08 16:08:42 +00:00
sh4 include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
sparc target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc 2024-02-03 23:43:50 +00:00
tricore include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
xtensa include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
Kconfig
meson.build target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00
target-common.c target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00