qemu-e2k

History

Aurelien Jarno d17bd1d8cc tcg/arm: fix TLB access in qemu-ld/st ops The TCG arm backend considers likely that the offset to the TLB entries does not exceed 12 bits for mem_index = 0. In practice this is not true for at least the MIPS target. The current patch fixes that by loading the bits 23-12 with a separate instruction, and using loads with address writeback, independently of the value of mem_idx. In total this allow a 24-bit offset, which is a lot more than needed. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>	2012-11-24 13:19:53 +01:00
..
tcg-target.c	tcg/arm: fix TLB access in qemu-ld/st ops	2012-11-24 13:19:53 +01:00
tcg-target.h	Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu	2012-10-19 20:28:22 +02:00

Aurelien Jarno d17bd1d8cc tcg/arm: fix TLB access in qemu-ld/st ops

The TCG arm backend considers likely that the offset to the TLB
entries does not exceed 12 bits for mem_index = 0. In practice this is
not true for at least the MIPS target.

The current patch fixes that by loading the bits 23-12 with a separate
instruction, and using loads with address writeback, independently of
the value of mem_idx. In total this allow a 24-bit offset, which is a
lot more than needed.

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-stable@nongnu.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

2012-11-24 13:19:53 +01:00

tcg-target.c

tcg/arm: fix TLB access in qemu-ld/st ops

2012-11-24 13:19:53 +01:00

tcg-target.h

Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu

2012-10-19 20:28:22 +02:00