93739075d2
In the MPS2 FPGAIO, PSCNTR is a free-running downcounter with a reload value configured via the PRESCALE register, and COUNTER counts up by 1 every time PSCNTR reaches zero. Implement these counters. We can just increment the counters migration subsection's version ID because we only added it in the previous commit, so no released QEMU versions will be using it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-3-peter.maydell@linaro.org
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* ARM MPS2 FPGAIO emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the FPGAIO register block in the AN505
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* FPGA image for the MPS2 dev board; it is documented in the
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* application note:
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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*/
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#ifndef MPS2_FPGAIO_H
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#define MPS2_FPGAIO_H
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#include "hw/sysbus.h"
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#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
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#define MPS2_FPGAIO(obj) OBJECT_CHECK(MPS2FPGAIO, (obj), TYPE_MPS2_FPGAIO)
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t led0;
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uint32_t prescale;
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uint32_t misc;
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/* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synced */
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int64_t pscntr_sync_ticks;
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/* Values of COUNTER and PSCNTR at time pscntr_sync_ticks */
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uint32_t counter;
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uint32_t pscntr;
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uint32_t prescale_clk;
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/* These hold the CLOCK_VIRTUAL ns tick when the CLK1HZ/CLK100HZ was zero */
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int64_t clk1hz_tick_offset;
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int64_t clk100hz_tick_offset;
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} MPS2FPGAIO;
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#endif
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