qemu-e2k/include/exec
Alex Bennée d25f2a7227 accel/tcg/translate-all: expand cpu_restore_state addr check
We are still seeing signals during translation time when we walk over
a page protection boundary. This expands the check to ensure the host
PC is inside the code generation buffer. The original suggestion was
to check versus tcg_ctx.code_gen_ptr but as we now segment the
translation buffer we have to settle for just a general check for
being inside.

I've also fixed up the declaration to make it clear it can deal with
invalid addresses. A later patch will fix up the call sites.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20171108153245.20740-2-alex.bennee@linaro.org
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-13 13:55:27 +00:00
..
user linux-user: Use correct alignment for long long on i386 guests 2016-08-04 16:34:59 +03:00
address-spaces.h Clean up header guards that don't match their file name 2016-07-12 16:19:16 +02:00
cpu_ldst_template.h trace: switch to modular code generation for sub-directories 2017-01-31 17:11:18 +00:00
cpu_ldst_useronly_template.h trace: switch to modular code generation for sub-directories 2017-01-31 17:11:18 +00:00
cpu_ldst.h cpu_ldst.h: use correct guest address parameter 2016-11-22 23:26:51 +01:00
cpu-all.h accel/tcg: allow to invalidate a write TLB entry immediately 2017-10-20 13:32:10 +02:00
cpu-common.h cpu: Introduce a wrapper for tlb_flush() that can be used in common code 2017-07-04 14:30:03 +02:00
cpu-defs.h cputlb: bring back tlb_flush_count under !TLB_DEBUG 2017-10-10 07:37:10 -07:00
cputlb.h cputlb: bring back tlb_flush_count under !TLB_DEBUG 2017-10-10 07:37:10 -07:00
exec-all.h accel/tcg/translate-all: expand cpu_restore_state addr check 2017-11-13 13:55:27 +00:00
gdbstub.h gdbstub: rename cpu_index -> cpu_gdb_index 2017-07-14 12:04:41 +02:00
gen-icount.h tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00
helper-gen.h tcg: Introduce tcgv_{i32,i64,ptr}_{arg,temp} 2017-10-24 21:47:46 +02:00
helper-head.h tcg: Remove GET_TCGV_* and MAKE_TCGV_* 2017-10-24 21:49:30 +02:00
helper-proto.h Clean up decorations and whitespace around header guards 2016-07-12 16:20:46 +02:00
helper-tcg.h tcg: Expand glue macros before stringifying helper names 2017-07-19 14:45:15 -07:00
hwaddr.h hw: Clean up includes 2016-06-07 18:19:23 +03:00
ioport.h hw: clean up hw/hw.h includes 2016-05-19 16:42:30 +02:00
log.h disas: Remove unused flags arguments 2017-10-25 11:55:09 +02:00
memattrs.h memory.h: Move MemTxResult type to memattrs.h 2017-09-04 15:21:54 +01:00
memory-internal.h memory: Rework "info mtree" to print flat views and dispatch trees 2017-09-21 23:19:38 +02:00
memory.h memory: trace FlatView creation and destruction 2017-09-22 01:06:51 +02:00
poison.h include/exec/poison: Mark CONFIG_SOFTMMU as poisoned 2017-07-04 14:39:11 +02:00
ram_addr.h migration: add bitmap for received page 2017-10-23 18:03:41 +02:00
ramlist.h ramblock: add new hmp command "info ramblock" 2017-05-17 17:31:16 +01:00
semihost.h semihosting: add --semihosting-config arg sub-argument 2015-06-19 14:17:45 +01:00
softmmu-semi.h Clean up decorations and whitespace around header guards 2016-07-12 16:20:46 +02:00
target_page.h migration: Make savevm.c target independent 2017-05-18 19:21:00 +02:00
tb-context.h tcg: take tb_ctx out of TCGContext 2017-10-24 13:53:42 -07:00
tb-hash-xx.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-hash.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
tb-lookup.h tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK 2017-10-24 13:53:41 -07:00
translator.h tcg: Add generic translation framework 2017-09-06 08:06:47 -07:00