Peter Maydell 5acc270a35 target/xtensa fixes for 5.1:
- fix access to special registers missing in the core configuration;
 - fix simcall opcode behavior for new hardware;
 - drop gen_io_end call from xtensa translator.
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Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging

target/xtensa fixes for 5.1:

- fix access to special registers missing in the core configuration;
- fix simcall opcode behavior for new hardware;
- drop gen_io_end call from xtensa translator.

# gpg: Signature made Thu 25 Jun 2020 09:08:58 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200625-xtensa:
  target/xtensa: drop gen_io_end call
  target/xtensa: fix simcall for newer hardware
  target/xtensa: fetch HW version from configuration overlay
  target/xtensa: work around missing SR definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-25 21:20:45 +01:00
..
2019-07-02 07:19:45 +02:00
2018-02-09 05:05:11 +01:00