Jonathan Cameron eb19d9079e cxl/cxl-host: Add memops for CFMWS region. ... These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the current implementation does not support: * switches * multiple HDM decoders at a given level. * unaligned accesses across the interleave boundaries Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-05-13 07:57:26 -04:00
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cxl_component.h	CXL/cxl_component: Add cxl_get_hb_cstate()	2022-05-13 07:57:26 -04:00
cxl_device.h	mem/cxl_type3: Add read and write functions for associated hostmem.	2022-05-13 07:57:26 -04:00
cxl_pci.h	hw/cxl/device: Add a memory device (8.2.8.5)	2022-05-13 06:13:36 -04:00
cxl.h	cxl/cxl-host: Add memops for CFMWS region.	2022-05-13 07:57:26 -04:00