qemu-e2k/include/hw/riscv
Nathaniel Graff 40061ac0bc
sifive_uart: Implement interrupt pending register
The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.

Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20 12:08:43 -08:00
..
riscv_hart.h
riscv_htif.h
sifive_clint.h RISC-V: Replace hardcoded constants with enum values 2018-05-06 10:39:38 +12:00
sifive_e.h hw/riscv/sifive_e: Create a SiFive E SoC object 2018-07-05 15:24:25 -07:00
sifive_plic.h RISC-V: Use atomic_cmpxchg to update PLIC bitmaps 2018-09-04 13:19:31 -07:00
sifive_prci.h SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.h SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.h sifive_u: Add clock DT node for GEM ethernet 2018-12-20 12:03:12 -08:00
sifive_uart.h sifive_uart: Implement interrupt pending register 2018-12-20 12:08:43 -08:00
spike.h RISC-V: Make some header guards more specific 2018-05-06 10:39:38 +12:00
virt.h hw/riscv/virt: Connect the gpex PCIe 2018-12-20 11:45:20 -08:00