e105db0227
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/*
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* Test m68k trap addresses.
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*/
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#define _GNU_SOURCE 1
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#include <signal.h>
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#include <assert.h>
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#include <limits.h>
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static int expect_sig;
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static int expect_si_code;
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static void *expect_si_addr;
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static greg_t expect_mc_pc;
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static volatile int got_signal;
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static void sig_handler(int sig, siginfo_t *si, void *puc)
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{
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ucontext_t *uc = puc;
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mcontext_t *mc = &uc->uc_mcontext;
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assert(sig == expect_sig);
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assert(si->si_code == expect_si_code);
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assert(si->si_addr == expect_si_addr);
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assert(mc->gregs[R_PC] == expect_mc_pc);
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got_signal = 1;
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}
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#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc)
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#define FMT0_STR(S) \
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"move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
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#define FMT2_STR(S) \
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"move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n"
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#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0)
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int main(int argc, char **argv)
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{
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struct sigaction act = {
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.sa_sigaction = sig_handler,
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.sa_flags = SA_SIGINFO
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};
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int t0, t1;
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sigaction(SIGILL, &act, NULL);
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sigaction(SIGTRAP, &act, NULL);
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sigaction(SIGFPE, &act, NULL);
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expect_sig = SIGFPE;
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expect_si_code = FPE_INTOVF;
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asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS);
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CHECK_SIG;
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#if 0
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/* FIXME: chk2 not correctly translated. */
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int bounds[2] = { 0, 1 };
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asm volatile(FMT2_STR("0:\tchk2.l %0, %1")
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: : "m"(bounds), "d"(2), FMT_INS);
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CHECK_SIG;
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#endif
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asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv")
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: : "d"(INT_MIN), "d"(1), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678")
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: : "d"(0), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq")
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: : "f"(0.0L), FMT_INS);
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CHECK_SIG;
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expect_si_code = FPE_INTDIV;
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asm volatile(FMT2_STR("0:\tdivs.w %1, %0")
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: "=d"(t0) : "d"(0), "0"(1), FMT_INS);
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CHECK_SIG;
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asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0")
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: "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS);
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CHECK_SIG;
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expect_sig = SIGILL;
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expect_si_code = ILL_ILLTRP;
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asm volatile(FMT0_STR("trap #1") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #2") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #3") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #4") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #5") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #6") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #7") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #8") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #9") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #10") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #11") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #12") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #13") : : FMT_INS);
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CHECK_SIG;
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asm volatile(FMT0_STR("trap #14") : : FMT_INS);
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CHECK_SIG;
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expect_sig = SIGTRAP;
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expect_si_code = TRAP_BRKPT;
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asm volatile(FMT0_STR("trap #15") : : FMT_INS);
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CHECK_SIG;
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return 0;
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}
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