qemu-e2k/target-arm
Peter Maydell d3afacc726 target-arm: Fix errors in writes to generic timer control registers
The code for handling writes to the generic timer control registers
had several bugs:
 * ISTATUS (bit 2) is read-only but we forced it to zero on any write
 * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where
   it should be '^'
 * the handling of IMASK was inverted: we should set the IRQ if
   ISTATUS is set and IMASK is clear, not if both are set

The combination of these bugs meant that when running a Linux guest
that uses the generic timers we would fairly quickly end up either
forgetting that the timer output should be asserted, or failing to
set the IRQ when the timer was unmasked. The result is that the guest
never gets any more timer interrupts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
2014-06-09 16:06:12 +01:00
..
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
arm-semi.c
cpu64.c target-arm: VFPv4 implies half-precision extension 2014-06-09 16:06:11 +01:00
cpu-qom.h
cpu.c target-arm: VFPv4 implies half-precision extension 2014-06-09 16:06:11 +01:00
cpu.h target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
crypto_helper.c target-arm: add support for v8 SHA1 and SHA256 instructions 2014-06-09 16:06:11 +01:00
gdbstub64.c
gdbstub.c
helper-a64.c target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: Fix errors in writes to generic timer control registers 2014-06-09 16:06:12 +01:00
helper.h target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
internals.h
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h
op_helper.c softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
translate-a64.c target-arm: A64: Implement two-register SHA instructions 2014-06-09 16:06:12 +01:00
translate.c target-arm: A32/T32: Mask CRC value in calling code, not helper 2014-06-09 16:06:12 +01:00
translate.h